On Tue, Nov 03, 2009 at 16:01:10, Sudhakar Rajashekhara wrote:
> On TI's DA830/OMAP-L137, DA850/OMAP-L138 and DM365, after
> setting the 4BITECC_ADD_CALC_START bit in the NAND Flash
> control register to 1 and before waiting for the NAND Flash
> status register to be equal to 1, 2 or 3, we have to wait
> till the ECC HW goes to correction state. Without this wait,
> ECC correction calculations will not be proper.
>
> This has been tested on DA830/OMAP-L137, DA850/OMAP-L138,
> DM355 and DM365 EVMs.
>
> Signed-off-by: Sudhakar Rajashekhara <[email protected]>
> Acked-by: Sneha Narnakaje <[email protected]>
> ---
> drivers/mtd/nand/davinci_nand.c | 16 ++++++++++++++++
> 1 files changed, 16 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
> index fe3eba8..8a32999 100644
> --- a/drivers/mtd/nand/davinci_nand.c
> +++ b/drivers/mtd/nand/davinci_nand.c
[...]
> +
> + /*
> + * ECC_STATE field reads 0x3 (Error correction complete) immediately
> + * after setting the 4BITECC_ADD_CALC_START bit. So if you immediately
> + * begin trying to poll for the state, you may fall right out of your
> + * loop without any of the correction calculations having taken place.
> + * The recommendation from the hardware team is to wait till ECC_STATE
> + * reads less than 4, which means ECC HW has entered correction state.
> + */
> + do {
> + ecc_state = (davinci_nand_readl(info,
> + NANDFSR_OFFSET) >> 8) & 0x0f;
> + cpu_relax();
> + } while (ecc_state < 4);
> +
Kevin,
David Woodhouse has suggested to add timeout in the above loop. I'll be
re-submitting
this patch soon.
Regards,
Sudhakar
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