On Fri, 9 Jul 2010 10:59:49 +0530
Sudhakar Rajashekhara <[email protected]> wrote:
> +
> + /*
> + * ECC_STATE field reads 0x3 (Error correction complete) immediately
> + * after setting the 4BITECC_ADD_CALC_START bit. So if you immediately
> + * begin trying to poll for the state, you may fall right out of your
> + * loop without any of the correction calculations having taken place.
> + * The recommendation from the hardware team is to wait till ECC_STATE
> + * reads less than 4, which means ECC HW has entered correction state.
> + */
> + do {
> + ecc_state = (davinci_nand_readl(info,
> + NANDFSR_OFFSET) >> 8) & 0x0f;
> + cpu_relax();
> + } while ((ecc_state < 4) && time_before(jiffies, timeo));
An up-to-100-milliseond busy wait is pretty bad. For how long do you
expect this to spin in practice?
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