On 11/29/2010 06:06 AM, Subhasish Ghosh wrote:
> The patch adds support for emulated UART controllers
> on the programmable realtime unit (PRU) available on OMAPL138.
> This defines the system resource requirements such as pin mux,
> clock, iomem, interrupt etc and registers the platform device
> as per the Linux driver model.
>
> Signed-off-by: Subhasish Ghosh <[email protected]>
> ---
> arch/arm/mach-davinci/board-da850-evm.c | 20 +++++
> arch/arm/mach-davinci/da850.c | 35 ++++++++-
> arch/arm/mach-davinci/devices-da8xx.c | 104
> ++++++++++++++++++++++++++-
> arch/arm/mach-davinci/include/mach/da8xx.h | 2 +
> arch/arm/mach-davinci/include/mach/memory.h | 1 +
> include/linux/serial_core.h | 3 +
> include/linux/ti_omapl_pru_suart.h | 38 ++++++++++
> 7 files changed, 198 insertions(+), 5 deletions(-)
> create mode 100644 include/linux/ti_omapl_pru_suart.h
>
> diff --git a/arch/arm/mach-davinci/board-da850-evm.c
> b/arch/arm/mach-davinci/board-da850-evm.c
> index f89b0b7..4ee09ed 100644
> --- a/arch/arm/mach-davinci/board-da850-evm.c
> +++ b/arch/arm/mach-davinci/board-da850-evm.c
> @@ -736,6 +736,26 @@ static struct edma_rsv_info *da850_edma_rsv[2] = {
> &da850_edma_cc1_rsv,
> };
>
> +static int __init da850_evm_setup_pru_suart(void)
> +{
> + int ret;
> +
> + if (!machine_is_davinci_da850_evm())
> + return 0;
> +
> + ret = davinci_cfg_reg_list(da850_pru_suart_pins);
> + if (ret)
> + pr_warning("da850_evm_init: da850_pru_suart_pins"
> + "mux setup failed: %d\n", ret);
> + ret = da8xx_register_pru_suart();
> + if (ret)
> + pr_warning("da850_evm_init: pru suart registration"
> + "failed: %d\n", ret);
> + return ret;
> +}
> +
> +device_initcall(da850_evm_setup_pru_suart);
> +
> static __init void da850_evm_init(void)
> {
> int ret;
> diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
> index 63916b9..a5eeb4f 100644
> --- a/arch/arm/mach-davinci/da850.c
> +++ b/arch/arm/mach-davinci/da850.c
> @@ -238,6 +238,13 @@ static struct clk tptc2_clk = {
> .flags = ALWAYS_ENABLED,
> };
>
> +static struct clk pru_clk = {
> + .name = "pru_ck",
> + .parent = &pll0_sysclk2,
> + .lpsc = DA8XX_LPSC0_DMAX,
> + .flags = ALWAYS_ENABLED,
> +};
> +
Wasn't this clock defined in the CAN patch as well?
> static struct clk uart0_clk = {
> .name = "uart0",
> .parent = &pll0_sysclk2,
> @@ -318,6 +325,14 @@ static struct clk mcasp_clk = {
> .flags = DA850_CLK_ASYNC3,
> };
>
> +static struct clk mcasp_pru_clk = {
> + .name = "mcasp_pru",
> + .parent = &pll0_sysclk2,
> + .lpsc = DA8XX_LPSC1_McASP0,
> + .gpsc = 1,
> + .flags = DA850_CLK_ASYNC3,
> +};
> +
> static struct clk lcdc_clk = {
> .name = "lcdc",
> .parent = &pll0_sysclk2,
> @@ -373,6 +388,7 @@ static struct clk_lookup da850_clks[] = {
> CLK(NULL, "tpcc1", &tpcc1_clk),
> CLK(NULL, "tptc2", &tptc2_clk),
> CLK(NULL, "uart0", &uart0_clk),
> + CLK(NULL, "pru_ck", &pru_clk),
> CLK(NULL, "uart1", &uart1_clk),
> CLK(NULL, "uart2", &uart2_clk),
> CLK(NULL, "aintc", &aintc_clk),
> @@ -382,6 +398,7 @@ static struct clk_lookup da850_clks[] = {
> CLK(NULL, "arm", &arm_clk),
> CLK(NULL, "rmii", &rmii_clk),
> CLK("davinci_emac.1", NULL, &emac_clk),
> + CLK(NULL, "mcasp_pru", &mcasp_pru_clk),
> CLK("davinci-mcasp.0", NULL, &mcasp_clk),
> CLK("da8xx_lcdc.0", NULL, &lcdc_clk),
> CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
> @@ -392,9 +409,13 @@ static struct clk_lookup da850_clks[] = {
>
> /*
> * Device specific mux setup
> - *
> - * soc description mux mode mode mux dbg
> - * reg offset mask mode
> + * soc -> DA850
> + * desc -> Pin name, which evaluates to soc##_##desc.
> + * muxreg -> Pin Multiplexing Control n (PINMUXn) Register
> number.
> + * mode_offset -> Bit offset in the register PINMUXn.
> + * mode_mask -> Number of bits for Pin Multiplexing Control n.
> + * mux_mode -> Multiplexing mode to set.
> + * dbg -> debug on/off
> */
> static const struct mux_config da850_pins[] = {
> #ifdef CONFIG_DAVINCI_MUX
> @@ -557,6 +578,14 @@ const short da850_uart0_pins[] __initdata = {
> -1
> };
>
> +const short da850_pru_suart_pins[] __initdata = {
> + DA850_AHCLKX, DA850_ACLKX, DA850_AFSX,
> + DA850_AHCLKR, DA850_ACLKR, DA850_AFSR,
> + DA850_AXR_13, DA850_AXR_9, DA850_AXR_7,
> + DA850_AXR_14, DA850_AXR_10, DA850_AXR_8,
> + -1
> +};
> +
> const short da850_uart1_pins[] __initdata = {
> DA850_UART1_RXD, DA850_UART1_TXD,
> -1
> diff --git a/arch/arm/mach-davinci/devices-da8xx.c
> b/arch/arm/mach-davinci/devices-da8xx.c
> index 9eec630..3ae9c3e 100644
> --- a/arch/arm/mach-davinci/devices-da8xx.c
> +++ b/arch/arm/mach-davinci/devices-da8xx.c
> @@ -14,7 +14,7 @@
> #include <linux/platform_device.h>
> #include <linux/dma-mapping.h>
> #include <linux/serial_8250.h>
> -
> +#include <linux/ti_omapl_pru_suart.h>
> #include <mach/cputype.h>
> #include <mach/common.h>
> #include <mach/time.h>
> @@ -85,7 +85,107 @@ struct platform_device da8xx_serial_device = {
> },
> };
>
> -static const s8 da8xx_queue_tc_mapping[][2] = {
> +
> +#define OMAPL138_PRU_MEM_BASE 0x01C30000
> +
> +#define OMAPL138_INT_PRU_SUART_1 IRQ_DA8XX_EVTOUT0
> +#define OMAPL138_INT_PRU_SUART_2 IRQ_DA8XX_EVTOUT1
> +#define OMAPL138_INT_PRU_SUART_3 IRQ_DA8XX_EVTOUT2
> +#define OMAPL138_INT_PRU_SUART_4 IRQ_DA8XX_EVTOUT3
> +#define OMAPL138_INT_PRU_SUART_5 IRQ_DA8XX_EVTOUT4
> +#define OMAPL138_INT_PRU_SUART_6 IRQ_DA8XX_EVTOUT5
> +#define OMAPL138_INT_PRU_SUART_7 IRQ_DA8XX_EVTOUT6
> +#define OMAPL138_INT_PRU_SUART_8 IRQ_DA8XX_EVTOUT7
It would be good to see how this stuff is being used by the driver. In
general, I think this patch, the CAN board patch, and the drivers should
belong to one series.
Thanks
- Cyril.
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