On Thu, Oct 25, 2012 at 6:11 PM, Murali Karicheri <[email protected]> wrote:
> This is the driver for the main PLL clock hardware found on DM SoCs. > This driver borrowed code from arch/arm/mach-davinci/clock.c and > implemented the driver as per common clock provider API. The main PLL > hardware typically has a multiplier, a pre-divider and a post-divider. > Some of the SoCs has the divider fixed meaning they can not be > configured through a register. HAS_PREDIV and HAS_POSTDIV flags are used > to tell the driver if a hardware has these dividers present or not. > Driver is configured through the struct clk_pll_data that has the > SoC specific clock data. > > Signed-off-by: Murali Karicheri <[email protected]> This looks good to me. Acked-by: Linus Walleij <[email protected]> Yours, Linus Walleij _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
