On Thu, Oct 25, 2012 at 6:11 PM, Murali Karicheri <[email protected]> wrote:
> pll dividers are present in the pll controller of DaVinci and Other > SoCs that re-uses the same hardware IP. This has a enable bit for > bypass the divider or enable the driver. This is a sub class of the > clk-divider clock checks the enable bit to calculare the rate and > invoke the recalculate() function of the clk-divider if enabled. > > Signed-off-by: Murali Karicheri <[email protected]> Looking good, Acked-by: Linus Walleij <[email protected]> Yours, Linus Walleij _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
