The branch main has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=6c5fdba45a63d66984e15ddc6996f5e88a55f22c
commit 6c5fdba45a63d66984e15ddc6996f5e88a55f22c Author: Andrew Turner <[email protected]> AuthorDate: 2026-01-23 14:31:04 +0000 Commit: Andrew Turner <[email protected]> CommitDate: 2026-01-23 17:02:29 +0000 arm/gic: Detect broken configurations Some virtualization platforms provide broken configurations. There is a GIC interrupt controller, however accessing the CPU interface registers leads to an external data abort. As these are needed to handle interrupts we are unable to boot further. Detect this misconfiguration and panic to tell the user the issue. Reviewed by: emaste Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D54832 --- sys/arm/arm/gic.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/sys/arm/arm/gic.c b/sys/arm/arm/gic.c index e33bda4886b9..64f19c848ea2 100644 --- a/sys/arm/arm/gic.c +++ b/sys/arm/arm/gic.c @@ -151,6 +151,8 @@ static struct arm_gic_softc *gic_sc = NULL; /* CPU Interface */ #define gic_c_read_4(_sc, _reg) \ bus_read_4((_sc)->gic_res[GIC_RES_CPU], (_reg)) +#define gic_c_peek_4(_sc, _reg, _val) \ + bus_peek_4((_sc)->gic_res[GIC_RES_CPU], (_reg), (_val)) #define gic_c_write_4(_sc, _reg, _val) \ bus_write_4((_sc)->gic_res[GIC_RES_CPU], (_reg), (_val)) /* Distributor Interface */ @@ -347,7 +349,18 @@ arm_gic_attach(device_t dev) goto cleanup; } - icciidr = gic_c_read_4(sc, GICC_IIDR); + /* + * Try accessing a CPU interface register. On some broken + * virtualization environments this will raise an external + * data abort. When this happens we can detect it using + * by peeking at the register & checking for the fault. + * As there is no way to continue with a normal boot we + * panic. + */ + if (gic_c_peek_4(sc, GICC_IIDR, &icciidr) != 0) + panic("Unable to access %s CPU registers, " + "broken hardware or hypervisor configuration", + device_get_nameunit(dev)); device_printf(dev, "pn 0x%x, arch 0x%x, rev 0x%x, implementer 0x%x irqs %u\n", GICD_IIDR_PROD(icciidr), GICD_IIDR_VAR(icciidr),
