This configures the CPT result address offset from WQE pointer
in RX_INLINE_CFG0. CPT result address offset is a signed
number in multiple of 16 bytes and configured to the
corresponding reserved space in packet meta area itself.
Signed-off-by: Rahul Bhansali <rbhans...@marvell.com>
---
Changes in v2: No change.
drivers/common/cnxk/roc_nix_inl.c | 27 ++++++++++++++++++++++++---
drivers/common/cnxk/roc_nix_inl_dev.c | 19 +++++++++++++++----
2 files changed, 39 insertions(+), 7 deletions(-)
diff --git a/drivers/common/cnxk/roc_nix_inl.c
b/drivers/common/cnxk/roc_nix_inl.c
index 6afdfb6b85..7e47151eee 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -399,6 +399,7 @@ nix_inl_inb_ipsec_sa_tbl_setup(struct roc_nix *roc_nix)
struct nix_inl_dev *inl_dev = NULL;
uint64_t max_sa, i, sa_pow2_sz;
uint64_t sa_idx_w, lenm1_max;
+ uint64_t res_addr_offset;
uint8_t profile_id = 0;
struct mbox *mbox;
size_t inb_sa_sz;
@@ -497,11 +498,16 @@ nix_inl_inb_ipsec_sa_tbl_setup(struct roc_nix *roc_nix)
def_cptq = inl_dev->nix_inb_qids[0];
}
+ res_addr_offset = (uint64_t)(inl_dev->res_addr_offset & 0xFF)
<< 48;
+ if (res_addr_offset)
+ res_addr_offset |= (1UL << 56);
+
lf_cfg->enable = 1;
lf_cfg->profile_id = profile_id; /* IPsec profile is 0th one */
lf_cfg->rx_inline_sa_base =
(uintptr_t)nix->inb_sa_base[profile_id];
- lf_cfg->rx_inline_cfg0 = ((def_cptq << 57) |
((uint64_t)SSO_TT_ORDERED << 44) |
- (sa_pow2_sz << 16) | lenm1_max);
+ lf_cfg->rx_inline_cfg0 =
+ ((def_cptq << 57) | res_addr_offset |
((uint64_t)SSO_TT_ORDERED << 44) |
+ (sa_pow2_sz << 16) | lenm1_max);
lf_cfg->rx_inline_cfg1 = (max_sa - 1) | (sa_idx_w << 32);
}
@@ -570,9 +576,13 @@ static int
nix_inl_reass_inb_sa_tbl_setup(struct roc_nix *roc_nix)
{
struct nix *nix = roc_nix_to_nix_priv(roc_nix);
+ struct idev_cfg *idev = idev_get_cfg();
struct nix_rx_inl_lf_cfg_req *lf_cfg;
+ struct nix_inl_dev *inl_dev = NULL;
uint64_t max_sa = 1, sa_pow2_sz;
uint64_t sa_idx_w, lenm1_max;
+ uint64_t res_addr_offset;
+ uint64_t def_cptq = 0;
size_t inb_sa_sz = 1;
uint8_t profile_id;
struct mbox *mbox;
@@ -612,11 +622,22 @@ nix_inl_reass_inb_sa_tbl_setup(struct roc_nix *roc_nix)
sa_idx_w = plt_log2_u32(max_sa);
lenm1_max = roc_nix_max_pkt_len(roc_nix) - 1;
+ if (idev && idev->nix_inl_dev) {
+ inl_dev = idev->nix_inl_dev;
+ if (inl_dev->nb_inb_cptlfs)
+ def_cptq =
inl_dev->nix_inb_qids[inl_dev->inb_cpt_lf_id];
+ }
+
+ res_addr_offset = (uint64_t)(inl_dev->res_addr_offset & 0xFF) << 48;
+ if (res_addr_offset)
+ res_addr_offset |= (1UL << 56);
+
lf_cfg->enable = 1;
lf_cfg->profile_id = profile_id;
lf_cfg->rx_inline_sa_base = (uintptr_t)nix->inb_sa_base[profile_id];
lf_cfg->rx_inline_cfg0 =
- (((uint64_t)SSO_TT_ORDERED << 44) | (sa_pow2_sz << 16) |
lenm1_max);
+ ((def_cptq << 57) | res_addr_offset | ((uint64_t)SSO_TT_ORDERED
<< 44) |
+ (sa_pow2_sz << 16) | lenm1_max);
lf_cfg->rx_inline_cfg1 = (max_sa - 1) | (sa_idx_w << 32);
rc = mbox_process(mbox);
diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c
b/drivers/common/cnxk/roc_nix_inl_dev.c
index 1db05741ad..1f071df8ea 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev.c
@@ -376,6 +376,7 @@ nix_inl_nix_ipsec_cfg(struct nix_inl_dev *inl_dev, bool ena)
}
} else {
struct nix_rx_inl_lf_cfg_req *lf_cfg;
+ uint64_t res_addr_offset;
uint64_t def_cptq;
lf_cfg = mbox_alloc_msg_nix_rx_inl_lf_cfg(mbox);
@@ -390,13 +391,17 @@ nix_inl_nix_ipsec_cfg(struct nix_inl_dev *inl_dev, bool
ena)
else
def_cptq =
inl_dev->nix_inb_qids[inl_dev->inb_cpt_lf_id];
+ res_addr_offset = (uint64_t)(inl_dev->res_addr_offset & 0xFF)
<< 48;
+ if (res_addr_offset)
+ res_addr_offset |= (1UL << 56);
+
lf_cfg->profile_id = inl_dev->ipsec_prof_id;
if (ena) {
lf_cfg->enable = 1;
lf_cfg->rx_inline_sa_base =
(uintptr_t)inl_dev->inb_sa_base[profile_id];
lf_cfg->rx_inline_cfg0 =
- ((def_cptq << 57) | ((uint64_t)SSO_TT_ORDERED
<< 44) |
- (sa_pow2_sz << 16) | lenm1_max);
+ ((def_cptq << 57) | res_addr_offset |
+ ((uint64_t)SSO_TT_ORDERED << 44) | (sa_pow2_sz
<< 16) | lenm1_max);
lf_cfg->rx_inline_cfg1 = (max_sa - 1) | (sa_w << 32);
} else {
lf_cfg->enable = 0;
@@ -611,6 +616,7 @@ nix_inl_nix_profile_config(struct nix_inl_dev *inl_dev,
uint8_t profile_id)
struct mbox *mbox = mbox_get((&inl_dev->dev)->mbox);
uint64_t max_sa, sa_w, sa_pow2_sz, lenm1_max;
struct nix_rx_inl_lf_cfg_req *lf_cfg;
+ uint64_t res_addr_offset;
uint64_t def_cptq;
size_t inb_sa_sz;
void *sa;
@@ -646,11 +652,16 @@ nix_inl_nix_profile_config(struct nix_inl_dev *inl_dev,
uint8_t profile_id)
else
def_cptq = inl_dev->nix_inb_qids[inl_dev->inb_cpt_lf_id + 1];
+ res_addr_offset = (uint64_t)(inl_dev->res_addr_offset & 0xFF) << 48;
+ if (res_addr_offset)
+ res_addr_offset |= (1UL << 56);
+
lf_cfg->enable = 1;
lf_cfg->profile_id = profile_id;
lf_cfg->rx_inline_sa_base = (uintptr_t)inl_dev->inb_sa_base[profile_id];
- lf_cfg->rx_inline_cfg0 = ((def_cptq << 57) | ((uint64_t)SSO_TT_ORDERED
<< 44) |
- (sa_pow2_sz << 16) | lenm1_max);
+ lf_cfg->rx_inline_cfg0 =
+ ((def_cptq << 57) | res_addr_offset | ((uint64_t)SSO_TT_ORDERED
<< 44) |
+ (sa_pow2_sz << 16) | lenm1_max);
lf_cfg->rx_inline_cfg1 = (max_sa - 1) | (sa_w << 32);
rc = mbox_process(mbox);
--
2.25.1
