The AMD hardware event handler could never run: the event interrupts
were never unmasked, their MSI-X vectors were never enabled and the
handler was only reached when no known doorbell was pending.
It also mishandled several simultaneous events and never cleared
the interrupt status.
Remove it, together with the now unused vendor operation and
register definitions, and document that hardware events are not
handled.
Fixes: d6dc5a7f8b06 ("raw/ntb: support AMD NTB")
Signed-off-by: Raghavendra Ningoji <[email protected]>
---
doc/guides/rawdevs/ntb.rst | 4 ++++
drivers/raw/ntb/ntb.c | 4 ----
drivers/raw/ntb/ntb.h | 3 ---
drivers/raw/ntb/ntb_hw_amd.c | 42 +-----------------------------------
drivers/raw/ntb/ntb_hw_amd.h | 21 ------------------
5 files changed, 5 insertions(+), 69 deletions(-)
diff --git a/doc/guides/rawdevs/ntb.rst b/doc/guides/rawdevs/ntb.rst
index 37328cd9e6..c4ad2f05c4 100644
--- a/doc/guides/rawdevs/ntb.rst
+++ b/doc/guides/rawdevs/ntb.rst
@@ -53,6 +53,10 @@ The AMD NTB hardware exposes two memory windows (BAR23 and
BAR45),
The scratchpad bank is split into two disjoint 8-register sets, one owned by
each side,
so the driver uses a packed handshake layout that fits within 8 registers.
+The AMD NTB hardware events (link up/down, peer reset, power state changes)
+are not handled: a peer going away is only detected through the doorbell
+handshake done when the peer device is stopped.
+
The AMD NTB uses an outbound translation window:
a write to a memory window offset is forwarded to ``(base | offset)`` in the
peer's memory
rather than ``(base + offset)``.
diff --git a/drivers/raw/ntb/ntb.c b/drivers/raw/ntb/ntb.c
index a1993121dd..d514ed669f 100644
--- a/drivers/raw/ntb/ntb.c
+++ b/drivers/raw/ntb/ntb.c
@@ -119,10 +119,6 @@ ntb_dev_intr_handler(void *param)
/* Clear other received doorbells. */
(*hw->ntb_ops->db_clear)(dev, db_bits);
-
- /* Let the vendor process any hardware-specific events. */
- if (hw->ntb_ops->handle_hw_event != NULL)
- (*hw->ntb_ops->handle_hw_event)(dev);
}
static void
diff --git a/drivers/raw/ntb/ntb.h b/drivers/raw/ntb/ntb.h
index 2787883160..2434997e84 100644
--- a/drivers/raw/ntb/ntb.h
+++ b/drivers/raw/ntb/ntb.h
@@ -102,8 +102,6 @@ enum ntb_spad_idx {
* @link_cleanup: Tear down the local scratchpad/translation state so the
* peer can no longer reach local memory.
* @mem_align: Base-address alignment required for a memory window memzone of
a given length.
- * @handle_hw_event: Optional. Process vendor-specific hardware events from
- * the common interrupt handler. May be NULL.
*/
struct ntb_dev_ops {
int (*ntb_dev_init)(const struct rte_rawdev *dev);
@@ -126,7 +124,6 @@ struct ntb_dev_ops {
int (*read_peer_config)(const struct rte_rawdev *dev);
void (*link_cleanup)(const struct rte_rawdev *dev);
uint64_t (*mem_align)(const struct rte_rawdev *dev, uint32_t mw_id,
uint64_t mw_len);
- void (*handle_hw_event)(const struct rte_rawdev *dev);
};
struct ntb_desc {
diff --git a/drivers/raw/ntb/ntb_hw_amd.c b/drivers/raw/ntb/ntb_hw_amd.c
index 64075501c2..47e4979619 100644
--- a/drivers/raw/ntb/ntb_hw_amd.c
+++ b/drivers/raw/ntb/ntb_hw_amd.c
@@ -445,7 +445,7 @@ static int
amd_ntb_vector_bind(const struct rte_rawdev *dev __rte_unused, uint8_t intr
__rte_unused,
uint8_t msix __rte_unused)
{
- /* Each doorbell/event maps to its MSI-X vector by default. */
+ /* Each doorbell maps to its MSI-X vector by default. */
return 0;
}
@@ -569,45 +569,6 @@ amd_ntb_link_cleanup(const struct rte_rawdev *dev)
amd_ntb_mw_set_trans(dev, i, 0, 0);
}
-/* Handle link/power-management events and acknowledge the SMU. Invoked from
- * the common interrupt handler when no inter-device doorbell is pending.
- */
-static void
-amd_ntb_handle_hw_event(const struct rte_rawdev *dev)
-{
- struct ntb_hw *ntb = dev->dev_private;
- uint32_t event, ack;
-
- event = rte_read32((char *)ntb->hw_addr + AMD_INTSTAT_OFFSET);
- event &= AMD_EVENT_INTMASK;
- if (event == 0)
- return;
-
- switch (event) {
- case AMD_PEER_FLUSH_EVENT:
- NTB_LOG(INFO, "Peer flush event.");
- break;
- case AMD_PEER_D0_EVENT:
- ack = rte_read32((char *)ntb->hw_addr + AMD_PMESTAT_OFFSET);
- if (ack & 0x1)
- NTB_LOG(INFO, "D0 wakeup completed for NTB.");
- /* fall through to ack the SMU */
- /* Falls through. */
- case AMD_PEER_RESET_EVENT:
- case AMD_LINK_DOWN_EVENT:
- case AMD_PEER_D3_EVENT:
- case AMD_PEER_PMETO_EVENT:
- case AMD_LINK_UP_EVENT:
- ack = rte_read32((char *)ntb->hw_addr + AMD_SMUACK_OFFSET);
- ack |= event;
- rte_write32(ack, (char *)ntb->hw_addr + AMD_SMUACK_OFFSET);
- break;
- default:
- NTB_LOG(ERR, "Unknown interrupt event 0x%" PRIx32, event);
- break;
- }
-}
-
static uint64_t
amd_ntb_get_mem_align(const struct rte_rawdev *dev __rte_unused, uint32_t
mw_id __rte_unused,
uint64_t mw_len)
@@ -634,5 +595,4 @@ const struct ntb_dev_ops amd_ntb_ops = {
.read_peer_config = amd_ntb_read_peer_config,
.link_cleanup = amd_ntb_link_cleanup,
.mem_align = amd_ntb_get_mem_align,
- .handle_hw_event = amd_ntb_handle_hw_event,
};
diff --git a/drivers/raw/ntb/ntb_hw_amd.h b/drivers/raw/ntb/ntb_hw_amd.h
index b03aed7d08..8fffa24348 100644
--- a/drivers/raw/ntb/ntb_hw_amd.h
+++ b/drivers/raw/ntb/ntb_hw_amd.h
@@ -16,7 +16,6 @@
#define AMD_MW_COUNT 2
#define AMD_DB_COUNT 16
#define AMD_SPAD_COUNT 16
-#define AMD_MSIX_VECTOR_COUNT 24
/* Peer register window: peer register = primary offset + 0x400. */
#define AMD_PEER_OFFSET 0x400
@@ -37,10 +36,6 @@
#define AMD_DBREQ_OFFSET 0x454 /* Doorbell request. */
#define AMD_DBMASK_OFFSET 0x45C /* Doorbell mask. */
#define AMD_DBSTAT_OFFSET 0x460 /* Doorbell status. */
-#define AMD_INTMASK_OFFSET 0x470 /* Interrupt mask. */
-#define AMD_INTSTAT_OFFSET 0x474 /* Interrupt status. */
-#define AMD_PMESTAT_OFFSET 0x480 /* PME status. */
-#define AMD_SMUACK_OFFSET 0x4A0 /* SMU control (PSMU_ACK). */
/* Link Status Register (0x408) bits, spec Table 5. */
#define AMD_SIDE_MASK (1 << 0) /* 0: primary, 1: secondary. */
@@ -50,22 +45,6 @@
#define AMD_SMM_REG_CTL (1 << 20)
#define AMD_PMM_REG_CTL (1 << 21)
-/* Interrupt Status/Mask event bits, spec Table 7. */
-#define AMD_PEER_FLUSH_EVENT (1 << 0)
-#define AMD_PEER_RESET_EVENT (1 << 1)
-#define AMD_PEER_D3_EVENT (1 << 2)
-#define AMD_PEER_PMETO_EVENT (1 << 3)
-#define AMD_PEER_D0_EVENT (1 << 4)
-#define AMD_LINK_UP_EVENT (1 << 5)
-#define AMD_LINK_DOWN_EVENT (1 << 6)
-#define AMD_EVENT_INTMASK (AMD_PEER_FLUSH_EVENT | \
- AMD_PEER_RESET_EVENT | \
- AMD_PEER_D3_EVENT | \
- AMD_PEER_PMETO_EVENT | \
- AMD_PEER_D0_EVENT | \
- AMD_LINK_UP_EVENT | \
- AMD_LINK_DOWN_EVENT)
-
/* PCIe link status decoding (link speed/width). */
#define AMD_LNK_STA_SPEED_MASK 0x000f
#define AMD_LNK_STA_WIDTH_MASK 0x03f0
--
2.34.1
