On Tue, Oct 31, 2017 at 06:21:33PM +0000, Matan Azrad wrote: > Replace most of the memory barriers by IO memory barriers since they > are all targeted to the DRAM; This improves code efficiency for > systems which force store order between different addresses. > > Only the doorbell register store should be protected by memory barrier > since it is targeted to the PCI memory domain. > > Limit pre byte count store IO memory barrier for systems with cache > line size smaller than 64B (TXBB size). > > This patch improves Tx performance by 0.2MPPS for one segment 64B > packets via 1 queue with 1 core test. > > Signed-off-by: Matan Azrad <ma...@mellanox.com>
Acked-by: Adrien Mazarguil <adrien.mazarg...@6wind.com> -- Adrien Mazarguil 6WIND
