> I'm attaching git diffs between the following two revisions:
> a: commit when BSD license text was added (mbed repo)
> b: first commit to the mynewt core repo.
>
> The Mynewt files are "b" in the attached diffs. That is, "+++" are
> changes added by Mynewt; "---" is removed by mbed.
Of course I attached the wrong diffs. Here are the correct ones.
Sorry about that!
Chris
diff --git
a/5b8ab176:libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis_nvic.c
b/e08882916788cee7cb2540604f8f6ec166a1c654:hw/bsp/nrf52pdk/src/cmsis_nvic.c
old mode 100644
new mode 100755
index 7889ed1..f05b2b6
---
a/5b8ab176:libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis_nvic.c
+++ b/e08882916788cee7cb2540604f8f6ec166a1c654:hw/bsp/nrf52pdk/src/cmsis_nvic.c
@@ -1,103 +1,53 @@
-/* mbed Microcontroller Library
- * CMSIS-style functionality to support dynamic vectors
-
*******************************************************************************
- * Copyright (c) 2011 ARM Limited. All rights reserved.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+/* mbed Microcontroller Library - cmsis_nvic for STM32F4
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
*
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
*******************************************************************************
+ * CMSIS-style functionality to support dynamic vectors
*/
-#include "cmsis_nvic.h"
-
-/* In the M0, there is no VTOR. In the LPC range such as the LPC11U,
- * whilst the vector table may only be something like 48 entries (192 bytes,
0xC0),
- * the SYSMEMREMAP register actually remaps the memory from
0x10000000-0x100001FF
- * to adress 0x0-0x1FF. In this case, RAM can be addressed at both 0x10000000
and 0x0
- *
- * If we just copy the vectors to RAM and switch the SYSMEMMAP, any accesses
to FLASH
- * above the vector table before 0x200 will actually go to RAM. So we need to
provide
- * a solution where the compiler gets the right results based on the memory map
- *
- * Option 1 - We allocate and copy 0x200 of RAM rather than just the table
- * - const data and instructions before 0x200 will be copied to and
fetched/exec from RAM
- * - RAM overhead: 0x200 - 0xC0 = 320 bytes, FLASH overhead: 0
- *
- * Option 2 - We pad the flash to 0x200 to ensure the compiler doesn't
allocate anything there
- * - No flash accesses will go to ram, as there will be nothing there
- * - RAM only needs to be allocated for the vectors, as all other ram
addresses are normal
- * - RAM overhead: 0, FLASH overhead: 320 bytes
- *
- * Option 2 is the one to go for, as RAM is the most valuable resource
- */
-
-
-#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Location of vectors in RAM
-#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in
flash
-/*
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
- uint32_t *vectors = (uint32_t*)SCB->VTOR;
- uint32_t i;
-
- // Copy and switch to dynamic vectors if the first time called
- if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
- uint32_t *old_vectors = vectors;
- vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
- for (i=0; i<NVIC_NUM_VECTORS; i++) {
- vectors[i] = old_vectors[i];
+#include "bsp/cmsis_nvic.h"
+
+extern char __isr_vector[];
+extern char __vector_tbl_reloc__[];
+
+void
+NVIC_Relocate(void)
+{
+ uint32_t *current_location;
+ uint32_t *new_location;
+ int i;
+
+ /*
+ * Relocate the vector table from its current position to the position
+ * designated in the linker script.
+ */
+ current_location = (uint32_t *)&__isr_vector;
+ new_location = (uint32_t *)&__vector_tbl_reloc__;
+
+ if (new_location != current_location) {
+ for (i = 0; i < NVIC_NUM_VECTORS; i++) {
+ new_location[i] = current_location[i];
}
- SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
}
- vectors[IRQn + 16] = vector;
-}
-uint32_t NVIC_GetVector(IRQn_Type IRQn) {
- uint32_t *vectors = (uint32_t*)SCB->VTOR;
- return vectors[IRQn + 16];
-}*/
+ /* Set VTOR */
+ SCB->VTOR = (uint32_t)&__vector_tbl_reloc__;
+}
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
- // int i;
- // Space for dynamic vectors, initialised to allocate in R/W
- static volatile uint32_t* vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
- /*
- // Copy and switch to dynamic vectors if first time called
- if((LPC_SYSCON->SYSMEMREMAP & 0x3) != 0x1) {
- uint32_t *old_vectors = (uint32_t *)0; // FLASH vectors are at
0x0
- for(i = 0; i < NVIC_NUM_VECTORS; i++) {
- vectors[i] = old_vectors[i];
- }
- LPC_SYSCON->SYSMEMREMAP = 0x1; // Remaps 0x0-0x1FF FLASH block to RAM
block
- }*/
+void
+NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors;
- // Set the vector
- vectors[IRQn + 16] = vector;
+ vectors = (uint32_t *)SCB->VTOR;
+ vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DMB();
}
-uint32_t NVIC_GetVector(IRQn_Type IRQn) {
- // We can always read vectors at 0x0, as the addresses are remapped
- uint32_t *vectors = (uint32_t*)0;
+uint32_t
+NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors;
- // Return the vector
- return vectors[IRQn + 16];
+ vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
}
+
diff --git
a/5b8ab176:libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis_nvic.h
b/e08882916788cee7cb2540604f8f6ec166a1c654:hw/bsp/nrf52pdk/include/bsp/cmsis_nvic.h
old mode 100644
new mode 100755
index e1fd1a3..78d0417
---
a/5b8ab176:libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis_nvic.h
+++
b/e08882916788cee7cb2540604f8f6ec166a1c654:hw/bsp/nrf52pdk/include/bsp/cmsis_nvic.h
@@ -1,48 +1,40 @@
-/* mbed Microcontroller Library
- * CMSIS-style functionality to support dynamic vectors
-
*******************************************************************************
- * Copyright (c) 2011 ARM Limited. All rights reserved.
- * All rights reserved.
+/**
+ * Copyright (c) 2015 Stack Inc.
*
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
*
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
*******************************************************************************
- */
+ * CMSIS-style functionality to support dynamic vectors
+ */
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
-#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
-#define NVIC_USER_IRQ_OFFSET 16
+#include <stdint.h>
-#include "nrf51822.h"
-#include "cmsis.h"
+#define NVIC_NUM_VECTORS (16 + 38) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+#include "nrf52xxx/nrf52.h"
#ifdef __cplusplus
extern "C" {
#endif
+void NVIC_Relocate(void);
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
uint32_t NVIC_GetVector(IRQn_Type IRQn);
