Yes I did. It seems that every SPI board already has this functionality... its working when I bypass the gate.
Verstuurd vanaf mijn iPhone > Op 12 jan. 2020 om 15:25 heeft Alan Carvalho de Assis <acas...@gmail.com> het > volgende geschreven: > > Hi Ben, > > I saw the circuit you sent privately to me. Actually you are using the > 74AHC1G125 as buffer to MISO signal, not MOSI as I was thinking. > > I see no reason it is not working, did you try to change the SPI frequency? > > BR, > > Alan > >> On 1/12/20, Alan Carvalho de Assis <acas...@gmail.com> wrote: >> Hi Ben, >> >> You need to describer better your issue and what you are trying to do. >> We cannot guess what is happening at your side. >> >> Normally the /CS should goes low before the SPI data transfer and >> should go high at end of the transfer. So if you are connecting it to >> 74AHC1G125 to /OE you should see the MOSI signal at the pin Y. >> >> Are you connecting the /CS at your other device that probably is >> connected to 74AHC1G125 ? >> >> BR, >> >> Alan >> >>> On 1/12/20, disruptivesolution...@gmail.com >>> <disruptivesolution...@gmail.com> wrote: >>> Why is the CS not pulled low at the end? So it can receive the last 0xFF? >>> >>> When I bypass the gate it is working.. Using the gate it is not? >>> >>> >>> >>> Thanks >>> >>> >>> >>> Ben >>> >>> >>> >>> >>
