In what way? I am concerned by a comment in the sama5 xdmac code which says:
“Calls to sam_dmatxsetup() and sam_dmarxsetup() must not be intermixed on the same transfer, however.” They are sort of intermixed as part of the SPI exchange function – which is near enough identical to most arm processors, though. From: Simon Filgis <si...@ingenieurbuero-filgis.de> D-Cache flush? -- Ingenieurbüro-Filgis USt-IdNr.: DE305343278 -- sent by mobile phone Tim Hardisty <t...@hardisty.co.uk<mailto:t...@hardisty.co.uk>> schrieb am Mi., 17. Mai 2023, 20:05: I am working on getting DMA working on the SPI peripheral of the SAMA5D2. DMA reads now work well, but the writes take absolutely forever…unless I have dma debug info enabled, when write transactions (to a GD25Q flash) do then work. I’m working through it, as it sounds like a race condition or other timing/sequence problem but if anyone by any chance has encountered anything similar, clues or suggestions would be most welcome! Thx, Tim
