This may depend on whether it's a SAMA5D2 or D3 or D4?
I only have experience of the SAMA5D2 and I think this is messed up in a
more subtle way for that device. There is essentially only 1 internal
SRAM available which is:
* 256k id L2 cache is disabled or
* 128k when L2 cache is enabled.
From the SAMA5D2 datasheet:
/The SAMA5D2 embeds a total of 128 Kbytes of high-speed SRAM. After
reset, and until the Remap command is/
/performed, the SRAM is accessible at address 0x0020 0000. When the
AXI Bus Matrix is remapped, the SRAM is/
/also available at address 0x0./
/
/
/The device features a second 128-Kbyte SRAM that can be allocated
either to the L2 cache controller or used as/
/an internal SRAM. After reset, this block is connected to the
system SRAM, making the two 128-Kbyte RAMs/
/contiguous. The SRAM_SEL bit, located in the SFR_L2CC_HRAMC
register, is used to reassign this memory as a/
/L2 cache memory./
Although I have boards I am currently not able to do any work, for
personal reasons, so I can't check any of this for real.
On 09/04/2026 16:12, Peter Barada wrote:
I ran builds over all of arm with increased warnings (-Wall -Wextra
-Wsystem-headers -Wformat
-Wno-unused-parameter -Wno-missing-field-initializers
-Wno-implicit-fallthrough) to see what warnings have been hidden turns
up redefinition warnings, one of which for all builds of giant-board,
jupiter-nano and sama5d2-xult boards:
include/arch/sama5/chip.h:106: warning: "SAM_ISRAM0_SIZE" redefined
Looking at include/arch/sama5/chip.h:
# define SAM_ISRAM0_SIZE (128*1024) /* SRAM0: 128KB */
#ifdef CONFIG_ARMV7A_L2CC_PL310
# define SAM_ISRAM1_SIZE (0) /* (SRAM1 used for L2 cache )*/
#else
# define SAM_ISRAM0_SIZE (64*1024) /* SRAM1: 128KB */
#endif
I think Greg[*] meant to at line 106 to define SAM_ISRAM1_SIZE instead
of SAM_ISRAM0_SIZE. Does this make sense? I don't have any of the
mentioned boards to test with, but can create a PR.
[*]
https://github.com/apache/nuttx/commit/831272cd35692cf3bec8a1bfd4f8fc3cc8f80dbb
