Sure, the patch sent. > -----Original Message----- > From: Liu, Zhiguang [mailto:zhiguang....@intel.com] > Sent: Tuesday, April 21, 2020 2:36 PM > To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist) > <abner.ch...@hpe.com> > Cc: Chen, Gilbert <gilbert.c...@hpe.com>; Leif Lindholm > <leif.lindh...@linaro.org>; Kinney, Michael D > <michael.d.kin...@intel.com>; Gao, Liming <liming....@intel.com> > Subject: RE: [edk2-devel] [PATCH v1 5/9] MdePkg/BaseIoLibIntrinsic: > Rename IoLibArm.c=>IoLibNoIo.c > > Hi Abner, > > In BaseIoLibIntrinsic.inf, you add the line "This I/O library only provides > non > I/O read and write." > I supposed this is a description for ARM and RISC-V but not for other arch. If > so, please specify it because this is an inf files all arch are using. > > Thanks > Zhiguang > > -----Original Message----- > From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Abner > Chang > Sent: Friday, April 10, 2020 3:21 PM > To: devel@edk2.groups.io > Cc: abner.ch...@hpe.com; Gilbert Chen <gilbert.c...@hpe.com>; Leif > Lindholm <leif.lindh...@linaro.org>; Kinney, Michael D > <michael.d.kin...@intel.com>; Gao, Liming <liming....@intel.com> > Subject: [edk2-devel] [PATCH v1 5/9] MdePkg/BaseIoLibIntrinsic: Rename > IoLibArm.c=>IoLibNoIo.c > > RISC-V MMIO library instance. > IoLibArm.c in fact implements a generic Mmio-only (and ANSI C compliant), > so rename it to better reflect this. > > Signed-off-by: Abner Chang <abner.ch...@hpe.com> > Co-authored-by: Gilbert Chen <gilbert.c...@hpe.com> > Reviewed-by: Leif Lindholm <leif.lindh...@linaro.org> > > Cc: Michael D Kinney <michael.d.kin...@intel.com> > Cc: Liming Gao <liming....@intel.com> > Cc: Leif Lindholm <leif.lindh...@linaro.org> > Cc: Gilbert Chen <gilbert.c...@hpe.com> > --- > .../BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf | 12 ++++++++---- > .../BaseIoLibIntrinsic/{IoLibArm.c => IoLibNoIo.c} | 4 +++- > 2 files changed, 11 insertions(+), 5 deletions(-) rename > MdePkg/Library/BaseIoLibIntrinsic/{IoLibArm.c => IoLibNoIo.c} (94%) > > diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf > b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf > index 457cce9378..cc23b6b227 100644 > --- a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf > +++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf > @@ -4,11 +4,12 @@ > # I/O Library that uses compiler intrinsics to perform IN and OUT > instructions > > # for IA-32 and x64. On IPF, I/O port requests are translated into MMIO > requests. > > # MMIO requests are forwarded directly to memory. For EBC, I/O port > requests > > -# ASSERT(). > > +# ASSERT(). This I/O library only provides non I/O read and write. > > # > > # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR> > > # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> > > # Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> > > +# Portions Copyright (c) 2020, Hewlett Packard Enterprise Development > +LP. All rights reserved.<BR> > > # > > # SPDX-License-Identifier: BSD-2-Clause-Patent > > # > > @@ -25,7 +26,7 @@ > > > > > # > > -# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 > > +# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64 > > # > > > > [Sources] > > @@ -50,10 +51,13 @@ > IoLib.c > > > > [Sources.ARM] > > - IoLibArm.c > > + IoLibNoIo.c > > > > [Sources.AARCH64] > > - IoLibArm.c > > + IoLibNoIo.c > > + > > +[Sources.RISCV64] > > + IoLibNoIo.c > > > > [Packages] > > MdePkg/MdePkg.dec > > diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibArm.c > b/MdePkg/Library/BaseIoLibIntrinsic/IoLibNoIo.c > similarity index 94% > rename from MdePkg/Library/BaseIoLibIntrinsic/IoLibArm.c > rename to MdePkg/Library/BaseIoLibIntrinsic/IoLibNoIo.c > index c6b822461d..a107136a74 100644 > --- a/MdePkg/Library/BaseIoLibIntrinsic/IoLibArm.c > +++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibNoIo.c > @@ -1,9 +1,11 @@ > /** @file > > - I/O Library for ARM. > > + I/O library for non I/O read and write access (memory map I/O read > + and > > + write only) architecture, such as ARM and RISC-V processor. > > > > Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR> > > Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> > > Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> > > + Copyright (c) 2020, Hewlett Packard Enterprise Development LP. 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