Abner:

> -----Original Message-----
> From: Chang, Abner (HPS SW/FW Technologist) <abner.ch...@hpe.com>
> Sent: Tuesday, April 21, 2020 9:05 AM
> To: devel@edk2.groups.io; Gao, Liming <liming....@intel.com>
> Subject: RE: [edk2-devel] [PATCH v1 0/9] MdePkg changes for RISC-V edk2 port
> 
> 
> 
> > -----Original Message-----
> > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> > Liming Gao
> > Sent: Tuesday, April 21, 2020 8:55 AM
> > To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> > <abner.ch...@hpe.com>
> > Subject: Re: [edk2-devel] [PATCH v1 0/9] MdePkg changes for RISC-V edk2
> > port
> >
> > Abner:
> >   Here is my minor comments.
> > 1.  For RISC-V processor related definitions, have they been defined in 
> > public
> > definitions?
> Are you referring to RiscV.h, RiscVOpenSbi.h and the corresponding spec? 
> Those are defined in RISC-V privilege spec and RISC-V SBI
> spec (not all of definitions).
> 
I want to confirm whether the change in UefiSpec.h has been defined in public 
UEFI spec. 

> > 2.  For MdePkg/BaseSynchronizationLib, why name file
> > SynchronizationAsm.S? Can it name to Synchronization.S?
> Hmm... I have no idea about why I named  it this way hahah...Yes. we can name 
> it as Synchronization.S.  I will resend the patches
> once you give comments on all patches? Or you already done the review?
> >
> > Thanks
> > Liming
> > -----Original Message-----
> > From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Chang,
> > Abner (HPS SW/FW Technologist)
> > Sent: 2020年4月10日 15:21
> > To: devel@edk2.groups.io
> > Cc: Chang, Abner (HPS SW/FW Technologist) <abner.ch...@hpe.com>
> > Subject: [edk2-devel] [PATCH v1 0/9] MdePkg changes for RISC-V edk2 port
> >
> > MdePkg modules and definitionsfor RISC-V architecture on edk2.
> >
> > BZ for entire RISC-V edk2 port,
> > https://urldefense.proofpoint.com/v2/url?u=https-
> > 3A__bugzilla.tianocore.org_show-5Fbug.cgi-3Fid-
> > 3D2672&d=DwIFAg&c=C5b8zRQO1miGmBeVZ2LFWg&r=_SN6FZBN4Vgi4Ulks
> > kz6qU3NYRO03nHp9P7Z5q59A3E&m=i2pc5cGhlgc-
> > Pd56r1673_LslTQbDe_XaFESUeh4tsE&s=m6Rw9jDskrzU3JlGDX4TQOji5DrEKO
> > 6wGXu5-OqkReY&e=
> >
> > These commits are verified by below PR,
> > https://github.com/tianocore/edk2/pull/512
> >
> > Abner Chang (9):
> >   MdePkg: RISC-V RV64 binding in MdePkg
> >   MdePkg/Include: RISC-V definitions.
> >   MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor.
> >   MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance
> >     implementation.
> >   MdePkg/BaseIoLibIntrinsic: Rename IoLibArm.c=>IoLibNoIo.c
> >   MdePkg/BasePeCoff: Add RISC-V PE/Coff related code.
> >   MdePkg/BaseCpuLib: RISC-V Base CPU library implementation.
> >   MdePkg/BaseSynchronizationLib: RISC-V cache related code.
> >   MdePkg/BaseSafeIntLib: Add RISCV64 arch for BaseSafeIntLib.
> >
> >  MdePkg/MdePkg.dec                             |   5 +-
> >  MdePkg/MdePkg.dsc                             |   3 +-
> >  .../BaseCacheMaintenanceLib.inf               |   4 +
> >  MdePkg/Library/BaseCpuLib/BaseCpuLib.inf      |   6 +-
> >  .../BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf |  12 +-
> >  MdePkg/Library/BaseLib/BaseLib.inf            |  18 +-
> >  .../Library/BasePeCoffLib/BasePeCoffLib.inf   |   5 +
> >  .../Library/BaseSafeIntLib/BaseSafeIntLib.inf |   6 +-
> >  .../BaseSynchronizationLib.inf                |   5 +
> >  MdePkg/Include/IndustryStandard/PeImage.h     |  12 +
> >  MdePkg/Include/Library/BaseLib.h              |  26 ++
> >  MdePkg/Include/Protocol/DebugSupport.h        |  55 ++++
> >  MdePkg/Include/Protocol/PxeBaseCode.h         |   4 +
> >  MdePkg/Include/RiscV64/ProcessorBind.h        | 173 ++++++++++++
> >  MdePkg/Include/Uefi/UefiBaseType.h            |  13 +
> >  MdePkg/Include/Uefi/UefiSpec.h                |   5 +
> >  .../BasePeCoffLib/BasePeCoffLibInternals.h    |   9 +
> >  .../BaseCacheMaintenanceLib/RiscVCache.c      | 250 ++++++++++++++++++
> >  .../{IoLibArm.c => IoLibNoIo.c}               |   4 +-
> >  .../Library/BaseLib/RiscV64/CpuBreakpoint.c   |  27 ++
> >  MdePkg/Library/BaseLib/RiscV64/CpuPause.c     |  29 ++
> >  .../BaseLib/RiscV64/DisableInterrupts.c       |  24 ++
> >  .../BaseLib/RiscV64/EnableInterrupts.c        |  25 ++
> >  .../BaseLib/RiscV64/GetInterruptState.c       |  35 +++
> >  .../BaseLib/RiscV64/InternalSwitchStack.c     |  55 ++++
> >  MdePkg/Library/BaseLib/RiscV64/LongJump.c     |  32 +++
> >  MdePkg/Library/BasePeCoffLib/BasePeCoff.c     |   3 +-
> >  .../BasePeCoffLib/RiscV/PeCoffLoaderEx.c      | 133 ++++++++++
> >  MdePkg/Library/BaseCpuLib/BaseCpuLib.uni      |   5 +-
> >  MdePkg/Library/BaseCpuLib/RiscV/Cpu.S         |  19 ++
> >  MdePkg/Library/BaseLib/RiscV64/FlushCache.S   |  21 ++
> >  .../BaseLib/RiscV64/RiscVCpuBreakpoint.S      |  14 +
> >  .../Library/BaseLib/RiscV64/RiscVCpuPause.S   |  14 +
> >  .../Library/BaseLib/RiscV64/RiscVInterrupt.S  |  32 +++
> >  .../BaseLib/RiscV64/RiscVSetJumpLongJump.S    |  55 ++++
> >  .../Library/BasePeCoffLib/BasePeCoffLib.uni   |   2 +
> >  .../RiscV64/SynchronizationAsm.S              |  78 ++++++
> >  37 files changed, 1204 insertions(+), 14 deletions(-)  create mode 100644
> > MdePkg/Include/RiscV64/ProcessorBind.h
> >  create mode 100644
> > MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> >  rename MdePkg/Library/BaseIoLibIntrinsic/{IoLibArm.c => IoLibNoIo.c} (94%)
> > create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c
> >  create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuPause.c
> >  create mode 100644 MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c
> >  create mode 100644 MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c
> >  create mode 100644 MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c
> >  create mode 100644 MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c
> >  create mode 100644 MdePkg/Library/BaseLib/RiscV64/LongJump.c
> >  create mode 100644
> > MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
> >  create mode 100644 MdePkg/Library/BaseCpuLib/RiscV/Cpu.S
> >  create mode 100644 MdePkg/Library/BaseLib/RiscV64/FlushCache.S
> >  create mode 100644
> > MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S
> >  create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S
> >  create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S
> >  create mode 100644
> > MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S
> >  create mode 100644
> > MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S
> >
> > --
> > 2.25.0
> >
> >
> >
> >
> >
> > 
> 


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