Hi Rebecca,
++ Harb who can give more insights on this. FYI, the original concern is
https://edk2.groups.io/g/devel/message/98482
On 1/18/2023 1:21 AM, Rebecca Cran wrote:
On 1/17/23 09:40, Ard Biesheuvel wrote:
On Tue, 17 Jan 2023 at 13:55, Rebecca Cran<rebe...@quicinc.com> wrote:
I was under the impression that this is becoming a more standard format?
If this is not defined in an ARM spec somewhere, we shouldn't add it
to ArmPkg at this point.
From what I've found, the ARM specs such as the Arm Architecture
Reference Manual for A-profile architecture don't define the meaning
of the affinity fields? That appears to be left up to the individual
Arm core TRMs.
I think so. This might be silicon specific implementation.
Per Arm Armv8-A Architecture Registers
(https://developer.arm.com/documentation/ddi0595/2021-12/AArch64-Registers/MPIDR-EL1--Multiprocessor-Affinity-Register),
if I interpret correctly, the AFF0 will give core ID or thread ID based
on the MT bit in the MPIDR register.
I think we should remove the following definitions particularly for
getting core id and cluster in ArmPkg/Include/Library/ArmLib.h to avoid
the confusion to others
#define ARM_CORE_MASK ARM_CORE_AFF0
#define ARM_CLUSTER_MASK ARM_CORE_AFF1
#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
And, should support GET_AFFx like
#define ARM_MPIDR_GET_AFF0(Mpid) ((Mpid) & ARM_CORE_AFF0)
For silicon specific usage, it can abstract them to proper IDs like
#define XXX_GET_CORE_ID(Mpid) ARM_MPIDR_GET_AFF0(Mpid)
Thanks,
Nhi
For example, the Cortex-X2 TRM says:
Affinity level 0. This is the affinity level that is most significant
for determining PE behavior. Higher affinity
levels are increasingly less significant in determining PE behavior.
The assigned value of the MPIDR.{Aff2,
Aff1, Aff0} or AArch64-MPIDR_EL1.{Aff3, Aff2, Aff1, Aff0} set of
fields of each PE must be unique within the
system as a whole.
0b00000000
Only one thread.
Affinity level 1. See the description of Aff0 for more information.
Value read from the CPUID configuration pins. Identification number
for each CPU in an cluster counting from
zero.
Affinity level 2. See the description of Aff0 for more information.
The value will be determined by the CLUSTERIDAFF2 configuration pins.
Affinity level 3. See the description of Aff0 for more information.
The value will be determined by the CLUSTERIDAFF3 configuration pins.
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