On Wed, May 10, 2023 at 10:34 AM Ni, Ray <ray...@intel.com> wrote: > > Firmware chooses to use 5-level paging when the platform using this firmware > claims to boot 5-level paging OS only. > > Usually, firmware uses 4-level paging to keep maximum OS compability.
Hi Ray, So, what happens if I don't enable LA57, have a gazillion TB of memory (such that I go over the 128TB 47-bit AS limit). Will EFI never try to access memory up there and page fault? What happens to the OS/bootloader? If it asks for memory up there (for KASLR, etc)? Does the memory map pre-reserve those upper regions of memory that are not accessible using 4-level paging? I really fail to see the advantages of PML5 support in EFI fw at the moment, particularly as you can simply choose to start all your allocations lower down the memory map (where you can indeed access things), reserve the upper, inaccessible bits, and things Should Work? Unless you're keeping some MMIO ranges up there, in which case, the solution is probably hard. -- Pedro -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#104590): https://edk2.groups.io/g/devel/message/104590 Mute This Topic: https://groups.io/mt/98788948/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
