On Thu, Aug 20, 2026 at 08:25:30AM +0000, Ramkumar Santhanakrishnan wrote: > Hi > > I have a question about commit > ecb778d0ac62560aa172786ba19521f27bc3f650<https://github.com/tianocore/edk2/commit/ecb778d0ac62560aa172786ba19521f27bc3f650>, > which limits the MMIO window to 1/8 of the total physical address space.
> For a guest with 46-bit physical addressing, this gives an 8 TB MMIO > window. We cannot increase the guest physical address width or move to > 5-level paging due to compatibility constraints. With newer GPUs (up > to 512 GB VRAM each), 8 TB may be insufficient for passthrough of 8 > GPUs, mainly because each BAR requires base address alignment. So you need 1 TB address space per GPU because of alignment I assume? So 8 TB total, and then a bit more for the non-GPU devices (network, storage etc)? > We are evaluating increasing the MMIO window size. > Could you share the rationale for the 1/8 limit? I've made it depend on the total address space available so it scales up automatically (newer + larger machines get larger MMIO windows), hoping that this logic works unchanged for a while. Using 1/8 looked like a generous number when introduced, which was before GPUs and NPUs with huge device memory appeared on the market. > Do you see any concerns with changing it to 1/4, or making it > configurable from QEMU? It is configurable via fw_cfg as already mentioned in the thread. If this is not working for large window sizes this should be fixed. I don't expect problems when going from 1/8 to 1/4 as default size, so no concerns here. Feel free to open a PR (best with your test results in the description). take care, Gerd -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#122114): https://edk2.groups.io/g/devel/message/122114 Mute This Topic: https://groups.io/mt/120843033/21656 Group Owner: [email protected] Unsubscribe: https://edk2.groups.io/g/devel/unsub [[email protected]] -=-=-=-=-=-=-=-=-=-=-=-
