Hi, Austin Thank you for the patch. On Wed, Oct 22, 2025 at 6:00 PM <[email protected]> wrote:
> Date: Wed, 22 Oct 2025 11:46:19 +0900 > From: Austin Kim <[email protected]> > Subject: [Crash-utility] [PATCH] RISCV64: fix wrong information of PMD > and PTE - SA39(4K page) support > To: [email protected] > Cc: [email protected] > Message-ID: <aPhFe2nFOb1qlY8h@adminpc-PowerEdge-R7525> > Content-Type: text/plain; charset=us-ascii > > When running 'vtop address' command in RISC-V based vmcore, the base > address > without applying offset for PMD and PTE is displayed. This is not correct > address for PMD and PTE. > > This change looks good to me. So: Ack. BTW: I haven't seen any similar changes on 4level_4k and 5level_4k, isn't it necessary? Or can you also take a look? Thanks Lianbo > With this patch, the actual address for PMD and PTE with the valid offset > is printed: > > <Before> > crash> vtop 0xffffffff81c4f000 > VIRTUAL PHYSICAL > ffffffff81c4f000 41e4f000 > > PAGE DIRECTORY: ffffffff81c4f000 > PGD: ffffffff81c4fff0 => 4fffe801 > PMD: 000000013fffa000 => 00000000107800e7 > PTE: 41e00000 => ffffffff8166fea0 > > PTE PAGE: 0000000000000000 not present > > <After> > crash> vtop 0xffffffff81c4f000 > VIRTUAL PHYSICAL > ffffffff81c4f000 41e4f000 > > PAGE DIRECTORY: ffffffff81c4f000 > PGD: ffffffff81c4fff0 => 4fffe801 > PMD: 000000013fffa070 => 00000000107800e7 > PTE: 41e00278 => ffffffff8166fea0 > > PTE PAGE: 0000000000000000 not present > > Signed-off-by: Austin Kim <[email protected]> > --- > riscv64.c | 25 ++++++++++++------------- > 1 file changed, 12 insertions(+), 13 deletions(-) > > diff --git a/riscv64.c b/riscv64.c > index ef5c41d..6b89f0b 100644 > --- a/riscv64.c > +++ b/riscv64.c > @@ -630,9 +630,8 @@ static int > riscv64_vtop_3level_4k(ulong *pgd, ulong vaddr, physaddr_t *paddr, int > verbose) > { > ulong *pgd_ptr, pgd_val; > - ulong pmd_val; > - ulong pte_val, pte_pfn; > - ulong pt_phys; > + ulong pmd_base, pmd_addr, pmd_val; > + ulong pte_base, pte_addr, pte_val, pte_pfn; > > if (verbose) > fprintf(fp, "PAGE DIRECTORY: %lx\n", (ulong)pgd); > @@ -646,25 +645,25 @@ riscv64_vtop_3level_4k(ulong *pgd, ulong vaddr, > physaddr_t *paddr, int verbose) > if (!pgd_val) > goto no_page; > pgd_val &= PTE_PFN_PROT_MASK; > - pt_phys = (pgd_val >> _PAGE_PFN_SHIFT) << PAGESHIFT(); > + pmd_base = (pgd_val >> _PAGE_PFN_SHIFT) << PAGESHIFT(); > > /* PMD */ > - FILL_PMD(PAGEBASE(pt_phys), PHYSADDR, PAGESIZE()); > - pmd_val = ULONG(machdep->pmd + PAGEOFFSET(sizeof(pmd_t) * > - pmd_index_l3_4k(vaddr))); > + FILL_PMD(PAGEBASE(pmd_base), PHYSADDR, PAGESIZE()); > + pmd_addr = pmd_base + sizeof(pmd_t) * pmd_index_l3_4k(vaddr); > + pmd_val = ULONG(machdep->pmd + PAGEOFFSET(pmd_addr)); > if (verbose) > - fprintf(fp, " PMD: %016lx => %016lx\n", pt_phys, pmd_val); > + fprintf(fp, " PMD: %016lx => %016lx\n", pmd_addr, > pmd_val); > if (!pmd_val) > goto no_page; > pmd_val &= PTE_PFN_PROT_MASK; > - pt_phys = (pmd_val >> _PAGE_PFN_SHIFT) << PAGESHIFT(); > + pte_base = (pmd_val >> _PAGE_PFN_SHIFT) << PAGESHIFT(); > > /* PTE */ > - FILL_PTBL(PAGEBASE(pt_phys), PHYSADDR, PAGESIZE()); > - pte_val = ULONG(machdep->ptbl + PAGEOFFSET(sizeof(pte_t) * > - pte_index_l3_4k(vaddr))); > + FILL_PTBL(PAGEBASE(pte_base), PHYSADDR, PAGESIZE()); > + pte_addr = pte_base + sizeof(pmd_t) * pte_index_l3_4k(vaddr); > + pte_val = ULONG(machdep->ptbl + PAGEOFFSET(pte_addr)); > if (verbose) > - fprintf(fp, " PTE: %lx => %lx\n", pt_phys, pte_val); > + fprintf(fp, " PTE: %lx => %lx\n", pte_addr, pte_val); > if (!pte_val) > goto no_page; > pte_val &= PTE_PFN_PROT_MASK; > -- > 2.34.1 >
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