We want to port fedora for RISC-V with out compressed (RV64IMAFD) instructions.
We are from Centre for Development of Advanced Computing (C-DAC) India. We have implemented an Out-of order quad core RISC-V processor on FPGA. The processor is without compressed instructions. We want to port fedora for RISC-V with out compressed instructions. Please share the link if it is already ported, or give the guidelines on how to port. Regards, Sreenadh S. _______________________________________________ devel mailing list -- devel@lists.fedoraproject.org To unsubscribe send an email to devel-le...@lists.fedoraproject.org Fedora Code of Conduct: https://docs.fedoraproject.org/en-US/project/code-of-conduct/ List Guidelines: https://fedoraproject.org/wiki/Mailing_list_guidelines List Archives: https://lists.fedoraproject.org/archives/list/devel@lists.fedoraproject.org
