On Mon, Jan 13, 2025 at 10:48:42AM +0000, Daniel P. Berrangé wrote: > On Fri, Jan 10, 2025 at 01:45:44PM -0800, John Reiser wrote: > > > A vendor-independent x86-64 psABI > > > supplement defines four "microachitecture levels": `x86-64-v1` (the > > > baseline, our code targets this), `x86-64-v2` (+`SSE3`, CentoOS > > > targets this), `x86-64-v3` (+`AVX`), `x86-64-v4` (+`AVX512`) [1]. > > The levels are not explicit about the classification of a CPU that has > > AVX (128-bit xmm registers) but lacks AVX2 (256-bit ymm registers.) > > Lacking AVX2 means the CPU would NOT satisfy x86-64-v3. The Fedora change > just gives a high level example. The canonical specification is at > > https://gitlab.com/x86-psABIs/x86-64-ABI
Thanks. I added this link to the Change page. Zbyszek -- _______________________________________________ devel mailing list -- devel@lists.fedoraproject.org To unsubscribe send an email to devel-le...@lists.fedoraproject.org Fedora Code of Conduct: https://docs.fedoraproject.org/en-US/project/code-of-conduct/ List Guidelines: https://fedoraproject.org/wiki/Mailing_list_guidelines List Archives: https://lists.fedoraproject.org/archives/list/devel@lists.fedoraproject.org Do not reply to spam, report it: https://pagure.io/fedora-infrastructure/new_issue
