No, the methodology was already established. It uses a couple different Python code generators but they use an adhoc code generation strategy, and each tool generates Verilog differently.
The goal for next generation chip is to migrate all of these to a Migen back-end. As we migrate I will try to put non-proprietary parts (like Hamming code generator) into Migen itself. On Tue, Apr 21, 2015 at 9:19 AM, Sébastien Bourdeauducq <[email protected]> wrote: > On 04/21/2015 11:00 PM, Guy Hutchison wrote: > > The ASIC is doing very well. The first couple days after power-on were > > tense but bring up went well and all major functions are working - about > > as good as one can expect for first pass silicon. > > Cool! Does it contain parts designed with Migen already? > > Sébastien > >
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