---
mibuild/platforms/m1.py | 2 +-
mibuild/xilinx/programmer.py | 13 +++++++++----
2 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/mibuild/platforms/m1.py b/mibuild/platforms/m1.py
index 93e213b..b67d002 100644
--- a/mibuild/platforms/m1.py
+++ b/mibuild/platforms/m1.py
@@ -127,7 +127,7 @@ class Platform(XilinxPlatform):
XilinxPlatform.__init__(self, "xc6slx45-fgg484-2", _io)
def create_programmer(self):
- return UrJTAG("fjmem-m1.bit")
+ return UrJTAG(cable='milkymist', flash_proxy_basename="fjmem-m1.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
diff --git a/mibuild/xilinx/programmer.py b/mibuild/xilinx/programmer.py
index f1ee00e..ce7ca8a 100644
--- a/mibuild/xilinx/programmer.py
+++ b/mibuild/xilinx/programmer.py
@@ -15,17 +15,21 @@ def _run_urjtag(cmds):
class UrJTAG(GenericProgrammer):
needs_bitreverse = True
+ def __init__(self, cable, flash_proxy_basename=None):
+ GenericProgrammer.__init__(self, flash_proxy_basename)
+ self.cable = cable
+
def load_bitstream(self, bitstream_file):
- cmds = """cable milkymist
+ cmds = """cable {cable}
detect
pld load {bitstream}
quit
-""".format(bitstream=bitstream_file)
+""".format(bitstream=bitstream_file, cable=self.cable)
_run_urjtag(cmds)
def flash(self, address, data_file):
flash_proxy = self.find_flash_proxy()
- cmds = """cable milkymist
+ cmds = """cable {cable}
detect
pld load "{flash_proxy}"
initbus fjmem opcode=000010
@@ -33,7 +37,8 @@ frequency 6000000
detectflash 0
endian big
flashmem "{address}" "{data_file}" noverify
-""".format(flash_proxy=flash_proxy, address=address, data_file=data_file)
+""".format(flash_proxy=flash_proxy, address=address, data_file=data_file,
+ cable=self.cable)
_run_urjtag(cmds)
--
2.4.3.573.g4eafbef
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