---
 misoc/integration/soc_core.py | 2 ++
 misoc/interconnect/csr.py     | 9 +++++++++
 misoc/interconnect/csr_bus.py | 4 ++++
 3 files changed, 15 insertions(+)

diff --git a/misoc/integration/soc_core.py b/misoc/integration/soc_core.py
index 66c14c8..cb18b35 100644
--- a/misoc/integration/soc_core.py
+++ b/misoc/integration/soc_core.py
@@ -183,6 +183,8 @@ class SoCCore(Module):
             self.add_csr_region(name, (self.mem_map["csr"] + 0x800*mapaddr) | 
self.shadow_base, self.csr_data_width, csrs)
         for name, memory, mapaddr, mmap in self.csrbankarray.srams:
             self.add_csr_region(name + "_" + memory.name_override, 
(self.mem_map["csr"] + 0x800*mapaddr) | self.shadow_base, self.csr_data_width, 
memory)
+        for name, constant in self.csrbankarray.constants:
+            self.add_constant((name + "_" + constant.name).upper(), 
constant.value)
 
         # Interrupts
         for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)):
diff --git a/misoc/interconnect/csr.py b/misoc/interconnect/csr.py
index 8183b2e..5bfbbe1 100644
--- a/misoc/interconnect/csr.py
+++ b/misoc/interconnect/csr.py
@@ -12,6 +12,14 @@ class _CSRBase(DUID):
         self.size = size
 
 
+class CSRConstant(Constant):
+    def __init__(self, value, bits_sign=None, name=None):
+        Constant.__init__(self, value, bits_sign)
+        self.name = get_obj_var_name(name)
+        if self.name is None:
+            raise ValueError("Cannot extract CSR name from code, need to 
specify.")
+
+
 class CSR(_CSRBase):
     def __init__(self, size=1, name=None):
         _CSRBase.__init__(self, size, name)
@@ -131,6 +139,7 @@ def _make_gatherer(method, cls, prefix_cb):
 class AutoCSR:
     get_memories = _make_gatherer("get_memories", Memory, memprefix)
     get_csrs = _make_gatherer("get_csrs", _CSRBase, csrprefix)
+    get_constants = _make_gatherer("get_constants", CSRConstant, csrprefix)
 
 
 class GenericBank(Module):
diff --git a/misoc/interconnect/csr_bus.py b/misoc/interconnect/csr_bus.py
index 9799baa..ac30061 100644
--- a/misoc/interconnect/csr_bus.py
+++ b/misoc/interconnect/csr_bus.py
@@ -157,6 +157,7 @@ class CSRBankArray(Module):
     def scan(self, ifargs, ifkwargs):
         self.banks = []
         self.srams = []
+        self.constants = []
         for name, obj in xdir(self.source, True):
             if hasattr(obj, "get_csrs"):
                 csrs = obj.get_csrs()
@@ -178,6 +179,9 @@ class CSRBankArray(Module):
                     self.submodules += mmap
                     csrs += mmap.get_csrs()
                     self.srams.append((name, memory, mapaddr, mmap))
+            if hasattr(obj, "get_constants"):
+                for constant in obj.get_constants():
+                    self.constants.append((name, constant))
             if csrs:
                 mapaddr = self.address_map(name, None)
                 if mapaddr is None:
-- 
1.9.1

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