Hi, On Monday 25 January 2010 02:38:02 Adam Wang wrote: > Just feedback about last mail for other schematics. > > D, DDR SDRAM > From [1], the prototype is MT46V32M16P-5B:F TR, So a VDD = +2.6V > ±0.1V, VDDQ = +2.6V ±0.1V (DDR400) can be achieved, let R62 = 2K Ohm > to be the VDD/VDDQ. The -5B device is backward compatible with all > slower speed grades. The voltage range of -5B device operating at > slower speed grades is VDD = VDDQ = 2.5V ± 0.2V. During prototype > stage, maybe can let R62 = 2K to test DDR400/PC3200(3-3-3) at 200MHz > clock rate or don't want test?
The FPGA will also be powered from the 2.5V source (for VCCAUX); setting it to 2.6V reduces the VCCAUX margins to +25mV -225mV, which seems pretty tight. An alternative is to power VCCAUX with 3.3V (Spartan-6s allow two voltages and they are selected via a configuration option) but this increases the dissipation on the 3.3V regulator. I chose this DRAM part because it was easily available at DigiKey and backwards compatible with the others - not necessarily to run it with PC3200 timings. We can use a slower and cheaper part during production. It is unlikely that we reach 200MHz on Spartan-6, the maximum target frequency I'm thinking about is 166MHz (PC2700 timings). I think the easiest option is to forget completely about PC3200 timings and set the power to 2.5V. For your information, the system is currently working on development boards using PC1600 (100MHz) timings so there is no need for super-high speed DRAM. > E, USB > Two USB-B connectors, no current limit protect circuit for each 0.5A > or just driven from +5V power source? Yes, I forgot those. What would you recommend as current limiting devices? Polyswitch? > F, Video Input > 1, CAPY2 should connect to C198's positive polarity, see p98 of > ADV7181BBSTZ 2, the GND of C225 & C226 must be digital GND. True, will fix :) > 3, Can add 33 ohm on SDA & SCLK? Is this only for protection in case of signal contention? For this purpose, we can set the drive strength of the FPGA I/O to 2mA (there are no other devices on this I2C bus) which is even more efficient than the 33 ohm resistors which would limit the current to 10mA and requires no extra part. Of course, this assumes that the FPGA does not get misconfigured with a higher drive strength. Thanks for the review, Sébastien _______________________________________________ http://lists.milkymist.org/listinfo.cgi/devel-milkymist.org IRC: #milkym...@freenode Webchat: www.milkymist.org/irc.html Wiki: www.milkymist.org/wiki
