Hi Michael,
I think there are two problems with the IRQ code you proposed at
http://pastebin.com/z6G3yLDk:
FIRST PROBLEM
asm_do_IRQ is called from entry.S:
rcsr r1, IP
addi r2, sp, 4
calli asm_do_IRQ
Therefore, it gets ALL interrupts (masked or not). We should AND register IP
with register IM.
SECOND PROBLEM (assuming problem 1 is fixed)
1. let's assume IRQ0 and IRQ1 get asserted in the same clock cycle
2. asm_do_IRQ is called with vec=3 (IRQ1|IRQ0)
3. IRQ0 is masked
4. generic_handle_irq(0) is called - this enables interrupts globally
5. asm_do_IRQ is called again because of IRQ1 and the interrupts being re-
enabled
6. IRQ0 was masked by the first ISR run and therefore is not processed, but
IRQ1 was not and generic_handle_irq(1) is called
7. second ISR run is complete, control returns to the first ISR,
generic_handle_irq(0) completes
8. the first ISR runs again generic_handle_irq(1), which is incorrect
To fix those problems, I propose the following code:
http://github.com/tmatsuya/linux-2.6/commit/cbb8905cb15fb080728156f8ad185a60e57ebcb7
Do you see a particular reason for using the lm32_current_irq_mask "cache", or
is it just Theobroma's programmers being stupid?
Tell me if it works, I have been unable to test (travelling and no board).
Sébastien
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