Sébastien Bourdeauducq wrote:
Hi,
On Thursday 08 April 2010 17:20:11 Philip Pemberton wrote:
I've been playing around with a homebrew Mico32 SoC
In what type of memory is your code stored, and how is it connected to the CPU
bus?
It's an Altera M4K ROM megafunction, 1024x 32-bit words, tied straight
onto the instruction bus:
// boot ROM
wire [31:0] INSROM_DATA;
bootrom ROM (
.clock (MCLK),
.address (CPU_I_ADDR[9:2]),
.q (CPU_I_DATA_TO_CPU)
);
assign CPU_I_ACK = CPU_I_STB;
assign CPU_I_ERR = 1'b0;
assign CPU_I_RTY = 1'b0;
> Is there source code available for your homebrew SoC?
OK, here goes:
http://www.philpem.me.uk/temp/lm32_soc.tar.gz
That's a complete tarball of my working directory. If you're testing
under ISE, you don't need all the Verilog modules -- these should be enough:
de1_lm32_top
wb_pio_port
lm32/*
wb_conmax/*
(The UART, Flash and Size Bridge are optional)
It's built to run on an Altera DE1 (Cyclone II Starter Board) devkit, if
you've got one of those...
I will check on my board, but I am a bit surprised that such an obvious bug
could have slipped through. It could be a problem with the Wishbone slave
returning the wrong instruction (I made a mistake that caused a similar issue
when trying AEMB for the first time).
There isn't a Wishbone slave per se -- the ROM is tied straight onto the
address bus, and feeds data straight to the CPU's Ibus. Normally it goes
through some bus arbitration (the Opencores/asics.ws CONMAX arbiter)
first, but I've disabled that for debugging.
I've actually got some NOPs in there between the various parts of the
code, so if it's skipping instructions I should see it exec a NOP or two
in between; what I'm seeing is a consistent +1 on every BI instruction.
And I agree, it's an obvious error in the core and one that shouldn't
have slipped through... if Lattice are running any testbenches against
the core before releasing it.
Thanks,
--
Phil.
phil...@philpem.me.uk
http://www.philpem.me.uk/
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