Sébastien Bourdeauducq wrote:
// boot ROM
wire [31:0] INSROM_DATA;
bootrom ROM (
        .clock          (MCLK),
        .address        (CPU_I_ADDR[9:2]),
        .q                      (CPU_I_DATA_TO_CPU)
);
assign CPU_I_ACK = CPU_I_STB;
assign CPU_I_ERR = 1'b0;
assign CPU_I_RTY = 1'b0;

I will assume this is a synchronous ROM (since it has a clock signal).

Yep. Registered address input, async data output. The address is latched on a L->H clock edge.

See http://github.com/lekernel/milkymist/tree/master/cores/bram/ for an example of using synchronous memories with Wishbone.

D'aaargh!
Well that explains a lot!

I've just redone the ACK logic to introduce a 1tcy delay. That fixed it!
I've also asked Lattice to close the support ticket -- no sense wasting valuable engineering time on a problem that isn't down to their CPU core.

By the way, you should infer your memories (unless there is a synthesizer bug or lack of optimization, which sometimes happens). Using the FPGA vendor's clickodrome for that is a retarded idea. Wastes your time, makes your design uselessly complex, and locks your design to that vendor.

The problem is inferring memories with a set content on startup, i.e. ROMs. I'm not aware of a way to do that with Verilog short of a massive 'case' statement. The nice thing about M4K ROMs is that I can use SRecord to convert the binary file into a .MIF (Memory Initialization File) which Quartus will then read in at compile-time and load into the M4K.

From my experience with Mico32, the concerns about quality that I have are related to the GNU toolchain, the GNU/Linux port

Yeah, I've heard the bad things that were said about the Linux port... though from what I've heard the toolchain (or at least gcc 3.4 + patch and binutils 2.20.1) is quite stable. The Theobroma one OTOH...

> and GNU Autocrap.

Oh good! I'm not the only person that hates Autoconf and Automake! :)

I think the hardware design is really good (that cache issue doesn't count, the problem stems from Xst).

Which versions of ISE/Xst is that bug known to manifest on?

I'm just curious -- like I said, I've got a Xilinx dev board due some time next week (actually an Enterpoint Drigmorn2) so I'd like to know if the current version of ISE (11.5) is.. ahem.. "a little less than stable". :)

Thanks,
--
Phil.
phil...@philpem.me.uk
http://www.philpem.me.uk/
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