Hi,

> But you forgot:
> The Flash's A0 should be grounded (the flash datasheet says this pin becomes
> unused, but it's safer to ground it than to leave it floating), FPGA's A0
> should be connected to Flash's A1, FPGA A1 -> Flash A2, etc. (see
> configuration waveform on UG380 p.50).

Yes, the sch sent you has changed already. But I indeed forgot to
record in wiki, records[1] is done now. Thanks, Good reminder.

> L19/FB/0402 --> change footprint to 1206?
> OK, it could be a good idea to use the bigger ferrite bead (less DC
> resistance).

Right.

Another thing, do you have an easy test plan that testing each
bi-directive connections between chips on board? We called production
s/w to validate productive run. You can say this is a phase of "design
for manufacturing". I mean it's not whole fully function image to test
hardware, I just need a simple codes which can verify if chips working
well after mounted by smt machine. Since I am not familiar with s/w
side. This may need help from list.
Ex.
1, verify if all I/O chips(audio codec, vga encode, ddrram, flash,
midi, dmx512, etc.) connected well to fpga.
2, I may directly add Test Points for easy measurement/test purposes
for manufacturer/end user if you won't mind.

Thanks,
Adam

[1] http://en.qi-hardware.com/wiki/Milkymist_One_Schematic_Change_History
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