>>>>> "Sébastien" == Sébastien Bourdeauducq
>>>>> <[email protected]> writes:
Sébastien> Hi, I am using ISE Webpack 12.1, it's a free of charge
Sébastien> download from the Xilinx website.
Sébastien> The JTAG cable is "Platform Cable USB (DLC9/DLC10)".
Sébastien> By the way: * I have received the boards today * When powered
Sébastien> on, the standby current on 5V is 0.38A - that's high, but no
Sébastien> part gets significantly hot or burns. All the voltage levels
Sébastien> are measured good. We'll investigate the overcurrent issue
Sébastien> later - or maybe you could do that in parallel while I work
Sébastien> on the FPGA? * JTAG boundary scan works, the FPGA is
Sébastien> detected. * The FPGA can be programmed through JTAG. * A
Sébastien> test bitstream that blinks a LED works, which means that the
Sébastien> clock is OK too.
Congratulations!
B.t.w, for JTAG access you can also have a look at my xc3sprog at
sourceforge. It is command line, so it fits better in a Makefile than Xilinx
Impact. However for programming parallel flash, I have no bscan_bpi core
yet, and as my design contains a P33 nor flash, which prbably isn't
supported for BPI configuration, I won't have a target to test against soon.
--
Uwe Bonnes [email protected]
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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