Hi, On Monday 12 July 2010 10:24:59 Adam Wang wrote: > The #3 also "ever" but without test all current branches. So did that > injection test make damages inside Spartan-6 already? We didn't know > exactly then.
After PCBA #4 went into short-circuit and over-current, I removed the video chip and all the currents and voltages went back to normal. I was able to configure the FPGA, write the flash and run the demo firmware without problem. So the FPGA is not damaged. > 2), The total current(measured at DC plug cable side) of #1 & #4 after > video input patched is still around 0.6A. I didn't measure current > over 30s when 5V power on, so no chance to meet over-1A condition. Yes, it took a little while for the over-current condition to develop. It never appeared on non-reworked boards, even when leaving them powered for days. > 5), After power-on 5V, is there any codes running inside fpga started > between power up after 50ms and before 30s? No, in theory the FPGA could not detect a sync code in the flash (which was blank) and remained unconfigured. The problem isn't on the FPGA, it's on the video input. > This can be realized that the routed traces to fpga is at high > impedance status when you removed. It is the same conditions as > decoder set by default value at 8 bit mode in P[15:8] and the one we > met were at Three-state on P[7:0] without patched. Then all went back > and well are reasonable. So the next more checks on like Florian's > email said. The Altera DE2 board [1] leaves P[7:0] floating and connects P[15:8] to the FPGA (Altera Cyclone) without problem - just like what we are doing. > 7), There's a question: > The digital core of the ADV7181B can be shut down by using a pin > (PWRDN) and a bit (PWRDN). U21's pin30 PWRDN_N is always at HIGH.The > PDBP controls which of the two has the higher priority. By default, > the pin (PWRDN) is given priority. This allows the user to have the > ADV7181B powered down by default. So if you set PDBP bit to 1 > immediately though I2C after configuring fpga I/O firstly, we can know > if over current high again. --> this can use # 1 or #4 to test. I cannot configure the FPGA on a board that has developed the short-circuit condition. The 3.3V supply fails and the FPGA is disabled until I remove the video chip. Sébastien [1] ftp://ftp.altera.com/up/pub/Webdocs/DE2_UserManual.pdf (p.45) _______________________________________________ http://lists.milkymist.org/listinfo.cgi/devel-milkymist.org IRC: #milkym...@freenode Webchat: www.milkymist.org/irc.html Wiki: www.milkymist.org/wiki
