Hi, attached is the patch, which adds the jtag interface for LM32 using the BSCAN_SPARTAN6 primitive.
you can test it with urjtag: register DEBUG 11 instruction USER1 000010 DEBUG instruction USER1 shift ir dr 01110000000 shift dr should do a reset. for more commands have a look in the lm32_debug.v. Next thing is revive my lm32 target for openocd. -- michael
From ea7dbbefddb35240593865293c214dbeceb19499 Mon Sep 17 00:00:00 2001 From: Michael Walle <[email protected]> Date: Thu, 23 Sep 2010 23:24:26 +0200 Subject: [PATCH] add jtag interface for spartan 6 --- boards/milkymist-one/sources.mak | 3 +- cores/lm32/rtl/jtag_cores.v | 96 ++++++++++++++++++++++------------- cores/lm32/rtl/jtag_tap_spartan6.v | 28 ++++++++++ cores/lm32/rtl/lm32_top.v | 4 -- 4 files changed, 90 insertions(+), 41 deletions(-) create mode 100644 cores/lm32/rtl/jtag_tap_spartan6.v diff --git a/boards/milkymist-one/sources.mak b/boards/milkymist-one/sources.mak index 874d88c..36d9f09 100644 --- a/boards/milkymist-one/sources.mak +++ b/boards/milkymist-one/sources.mak @@ -20,7 +20,8 @@ LM32_SRC= \ $(CORES_DIR)/lm32/rtl/lm32_top.v \ $(CORES_DIR)/lm32/rtl/lm32_debug.v \ $(CORES_DIR)/lm32/rtl/lm32_jtag.v \ - $(CORES_DIR)/lm32/rtl/jtag_cores.v + $(CORES_DIR)/lm32/rtl/jtag_cores.v \ + $(CORES_DIR)/lm32/rtl/jtag_tap_spartan6.v FMLARB_SRC=$(wildcard $(CORES_DIR)/fmlarb/rtl/*.v) FMLBRG_SRC=$(wildcard $(CORES_DIR)/fmlbrg/rtl/*.v) CSRBRG_SRC=$(wildcard $(CORES_DIR)/csrbrg/rtl/*.v) diff --git a/cores/lm32/rtl/jtag_cores.v b/cores/lm32/rtl/jtag_cores.v index 7e1ba32..cbf20e2 100644 --- a/cores/lm32/rtl/jtag_cores.v +++ b/cores/lm32/rtl/jtag_cores.v @@ -1,36 +1,60 @@ -// TODO - -module jtag_cores ( - // ----- Inputs ------- - reg_d, - reg_addr_d, - // ----- Outputs ------- - reg_update, - reg_q, - reg_addr_q, - jtck, - jrstn -); - -input [7:0] reg_d; -input [2:0] reg_addr_d; - -output reg_update; -wire reg_update; -output [7:0] reg_q; -wire [7:0] reg_q; -output [2:0] reg_addr_q; -wire [2:0] reg_addr_q; - -output jtck; -wire jtck; -output jrstn; -wire jrstn; - -assign reg_update = 1'b0; -assign reg_q = 8'hxx; -assign reg_addr_q = 3'bxxx; -assign jtck = 1'b0; -assign jrstn = 1'b1; - -endmodule +module jtag_cores ( + input [7:0] reg_d, + input [2:0] reg_addr_d, + output reg_update, + output [7:0] reg_q, + output [2:0] reg_addr_q, + output jtck, + output jrstn +); + +wire sel; +wire tck; +wire tdi; +wire tdo; +wire shift; +wire update; +wire reset; + +jtag_tap jtag_tap ( + .sel(sel), + .tck(tck), + .tdi(tdi), + .tdo(tdo), + .shift(shift), + .update(update), + .reset(reset) +); + +reg [10:0] jtag_shift; +reg [10:0] jtag_latched; + +always @(posedge tck or posedge reset) +begin + if(reset) + jtag_shift <= 11'b0; + else begin + if(shift) + jtag_shift <= {tdi, jtag_shift[10:1]}; + else + jtag_shift <= {reg_d, reg_addr_d}; + end +end + +assign tdo = jtag_shift[0]; + +always @(posedge reg_update or posedge reset) +begin + if(reset) + jtag_latched <= 11'b0; + else + jtag_latched <= jtag_shift; +end + +assign reg_update = update & sel; +assign reg_q = jtag_latched[10:3]; +assign reg_addr_q = jtag_latched[2:0]; +assign jtck = tck; +assign jrstn = ~reset; + +endmodule diff --git a/cores/lm32/rtl/jtag_tap_spartan6.v b/cores/lm32/rtl/jtag_tap_spartan6.v new file mode 100644 index 0000000..21aff3a --- /dev/null +++ b/cores/lm32/rtl/jtag_tap_spartan6.v @@ -0,0 +1,28 @@ + +module jtag_tap( + output sel, + output tck, + output tdi, + input tdo, + output shift, + output update, + output reset +); + +BSCAN_SPARTAN6 #( + .JTAG_CHAIN(1) +) bscan ( + .CAPTURE(), + .DRCK(tck), + .RESET(reset), + .RUNTEST(), + .SEL(sel), + .SHIFT(shift), + .TCK(), + .TDI(tdi), + .TMS(), + .UPDATE(update), + .TDO(tdo) +); + +endmodule diff --git a/cores/lm32/rtl/lm32_top.v b/cores/lm32/rtl/lm32_top.v index 4ef1fbf..4444b23 100644 --- a/cores/lm32/rtl/lm32_top.v +++ b/cores/lm32/rtl/lm32_top.v @@ -293,16 +293,12 @@ lm32_cpu cpu ( // JTAG cores jtag_cores jtag_cores ( // ----- Inputs ----- -`ifdef INCLUDE_LM32 .reg_d (jtag_reg_d), .reg_addr_d (jtag_reg_addr_d), -`endif // ----- Outputs ----- -`ifdef INCLUDE_LM32 .reg_update (jtag_update), .reg_q (jtag_reg_q), .reg_addr_q (jtag_reg_addr_q), -`endif .jtck (jtck), .jrstn (jrstn) ); -- 1.7.1
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