On 07/03/11 04:21 PM, Sebastien Bourdeauducq wrote:
Yes, but in some cases, a synthesizer that supports retiming
Ok, I was under the impression the FPGA synthesis tools didn't do this
and it was more the domain of ASIC tools. Quartus clearly doesn't
support it (since I see an improvement by manually doing it).
For
example, this is a valid way to infer a 2-stage pipelined multiplier
with Xst, even if the operands are too large for a single hard
multiplier:
always @(posedge clk) begin
foo<= a*b;
bar<= foo; /* foo is not used anywhere else */
end
That's pretty cool if your tool can do it for you.
At any rate, if there are such smart FPGA synthesizers, then I can see
why you'd like to leave it as it is. For our stuff using Altera, I'll
just keep the change locally.
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