Before you can add a master device on the wishbone bus, you need make the CSR 5 Bits if you want to preserve all the already working devices on the SoC.
I attached a simple/small patch for that, it worked for me. Next step will be modify the wishbon bus (shared and swiched one) I'll keep you posted. Cristian Paul
diff --git a/cores/ac97/rtl/ac97_ctlif.v b/cores/ac97/rtl/ac97_ctlif.v
index 7d278c5..55a57fc 100644
--- a/cores/ac97/rtl/ac97_ctlif.v
+++ b/cores/ac97/rtl/ac97_ctlif.v
@@ -73,7 +73,7 @@ always @(posedge sys_clk) begin
dmaw_finished_r <= dmaw_finished;
end
-wire csr_selected = csr_a[13:10] == csr_addr;
+wire csr_selected = csr_a[14:10] == csr_addr;
reg request_en;
reg request_write;
diff --git a/cores/bt656cap/rtl/bt656cap_ctlif.v b/cores/bt656cap/rtl/bt656cap_ctlif.v
index 66f4e1b..5241292 100644
--- a/cores/bt656cap/rtl/bt656cap_ctlif.v
+++ b/cores/bt656cap/rtl/bt656cap_ctlif.v
@@ -55,7 +55,7 @@ assign sda = (sda_oe & ~sda_o) ? 1'b0 : 1'bz;
/* CSR IF */
-wire csr_selected = csr_a[13:10] == csr_addr;
+wire csr_selected = csr_a[14:10] == csr_addr;
reg [14:0] max_bursts;
reg [14:0] done_bursts;
diff --git a/cores/csrbrg/rtl/csrbrg.v b/cores/csrbrg/rtl/csrbrg.v
index da6799b..fbc6142 100644
--- a/cores/csrbrg/rtl/csrbrg.v
+++ b/cores/csrbrg/rtl/csrbrg.v
@@ -29,7 +29,7 @@ module csrbrg(
output reg wb_ack_o,
/* CSR */
- output reg [13:0] csr_a,
+ output reg [14:0] csr_a,
output reg csr_we,
output reg [31:0] csr_do,
input [31:0] csr_di
@@ -43,7 +43,7 @@ end
/* Datapath: CSR <- WB */
reg next_csr_we;
always @(posedge sys_clk) begin
- csr_a <= wb_adr_i[15:2];
+ csr_a <= wb_adr_i[16:2];
csr_we <= next_csr_we;
csr_do <= wb_dat_i;
end
diff --git a/cores/dmx/rtl/dmx_rx.v b/cores/dmx/rtl/dmx_rx.v
index 270f3a3..720ec3e 100644
--- a/cores/dmx/rtl/dmx_rx.v
+++ b/cores/dmx/rtl/dmx_rx.v
@@ -32,7 +32,7 @@ module dmx_rx #(
/* RAM and CSR interface */
-wire csr_selected = csr_a[13:10] == csr_addr;
+wire csr_selected = csr_a[14:10] == csr_addr;
wire [7:0] csr_channel;
reg [8:0] channel_a;
diff --git a/cores/dmx/rtl/dmx_tx.v b/cores/dmx/rtl/dmx_tx.v
index 3c8cc7e..0be637e 100644
--- a/cores/dmx/rtl/dmx_tx.v
+++ b/cores/dmx/rtl/dmx_tx.v
@@ -33,7 +33,7 @@ module dmx_tx #(
/* RAM and CSR interface */
-wire csr_selected = csr_a[13:10] == csr_addr;
+wire csr_selected = csr_a[14:10] == csr_addr;
wire csr_channels_we;
wire [31:0] csr_do_channels;
diff --git a/cores/fmlmeter/rtl/fmlmeter.v b/cores/fmlmeter/rtl/fmlmeter.v
index e8d41b9..e354803 100644
--- a/cores/fmlmeter/rtl/fmlmeter.v
+++ b/cores/fmlmeter/rtl/fmlmeter.v
@@ -42,7 +42,7 @@ reg en; // @ 00
reg [31:0] stb_count; // @ 04
reg [31:0] ack_count; // @ 08
-wire csr_selected = csr_a[13:10] == csr_addr;
+wire csr_selected = csr_a[14:10] == csr_addr;
always @(posedge sys_clk) begin
if(sys_rst) begin
diff --git a/cores/hpdmc_ddr32/rtl/hpdmc_ctlif.v b/cores/hpdmc_ddr32/rtl/hpdmc_ctlif.v
index d5c0cd5..83a5b3f 100644
--- a/cores/hpdmc_ddr32/rtl/hpdmc_ctlif.v
+++ b/cores/hpdmc_ddr32/rtl/hpdmc_ctlif.v
@@ -56,7 +56,7 @@ module hpdmc_ctlif #(
output reg idelay_cal
);
-wire csr_selected = csr_a[13:10] == csr_addr;
+wire csr_selected = csr_a[14:10] == csr_addr;
always @(posedge sys_clk) begin
if(sys_rst) begin
diff --git a/cores/memcard/rtl/memcard.v b/cores/memcard/rtl/memcard.v
index dd8b47c..bf27bf6 100644
--- a/cores/memcard/rtl/memcard.v
+++ b/cores/memcard/rtl/memcard.v
@@ -98,7 +98,7 @@ always @(posedge sys_clk) begin
mc_d_r2 <= mc_d_r1;
end
-wire csr_selected = csr_a[13:10] == csr_addr;
+wire csr_selected = csr_a[14:10] == csr_addr;
reg [2:0] cmd_bitcount;
reg [2:0] dat_bitcount;
diff --git a/cores/memtest/rtl/memtest.v b/cores/memtest/rtl/memtest.v
index a05562a..c19ef21 100644
--- a/cores/memtest/rtl/memtest.v
+++ b/cores/memtest/rtl/memtest.v
@@ -41,7 +41,7 @@ module memtest #(
wire rand_ce;
wire [63:0] rand;
-wire csr_selected = csr_a[13:10] == csr_addr;
+wire csr_selected = csr_a[14:10] == csr_addr;
wire load_nbursts = csr_selected & (csr_a[2:0] == 3'd0) & csr_we;
wire load_address = csr_selected & (csr_a[2:0] == 3'd2) & csr_we;
diff --git a/cores/minimac/rtl/minimac_ctlif.v b/cores/minimac/rtl/minimac_ctlif.v
index 3872e14..7fb85d9 100644
--- a/cores/minimac/rtl/minimac_ctlif.v
+++ b/cores/minimac/rtl/minimac_ctlif.v
@@ -99,7 +99,7 @@ assign rx_adr = {30{select0}} & slot0_adr
reg [10:0] tx_remaining;
assign tx_valid = |tx_remaining;
-wire csr_selected = csr_a[13:10] == csr_addr;
+wire csr_selected = csr_a[14:10] == csr_addr;
always @(posedge sys_clk) begin
if(sys_rst) begin
diff --git a/cores/pfpu/rtl/pfpu_ctlif.v b/cores/pfpu/rtl/pfpu_ctlif.v
index 0328fbd..228174c 100644
--- a/cores/pfpu/rtl/pfpu_ctlif.v
+++ b/cores/pfpu/rtl/pfpu_ctlif.v
@@ -76,7 +76,7 @@ reg [13:0] vertex_counter;
reg [10:0] collision_counter;
reg [10:0] stray_counter;
-wire csr_selected = csr_a[13:10] == csr_addr;
+wire csr_selected = csr_a[14:10] == csr_addr;
reg [31:0] csr_do_r;
reg csr_do_cont;
diff --git a/cores/rc5/rtl/rc5.v b/cores/rc5/rtl/rc5.v
index 6f48bae..052eb64 100644
--- a/cores/rc5/rtl/rc5.v
+++ b/cores/rc5/rtl/rc5.v
@@ -114,7 +114,7 @@ end
// CSR interface
//-----------------------------------------------------------------
-wire csr_selected = csr_a[13:10] == csr_addr;
+wire csr_selected = csr_a[14:10] == csr_addr;
always @(posedge sys_clk) begin
if(sys_rst) begin
diff --git a/cores/softusb/rtl/softusb_hostif.v b/cores/softusb/rtl/softusb_hostif.v
index 76fec4e..1c135b8 100644
--- a/cores/softusb/rtl/softusb_hostif.v
+++ b/cores/softusb/rtl/softusb_hostif.v
@@ -35,7 +35,7 @@ module softusb_hostif #(
input [5:0] io_a
);
-wire csr_selected = csr_a[13:10] == csr_addr;
+wire csr_selected = csr_a[14:10] == csr_addr;
reg usb_rst0;
diff --git a/cores/sysctl/rtl/sysctl.v b/cores/sysctl/rtl/sysctl.v
index 4a10689..569cc9b 100644
--- a/cores/sysctl/rtl/sysctl.v
+++ b/cores/sysctl/rtl/sysctl.v
@@ -102,7 +102,7 @@ sysctl_icap icap(
* Logic and CSR interface
*/
-wire csr_selected = csr_a[13:10] == csr_addr;
+wire csr_selected = csr_a[14:10] == csr_addr;
assign icap_we = csr_selected & csr_we & (csr_a[3:0] == 4'b1101);
diff --git a/cores/tmu2/rtl/tmu2_ctlif.v b/cores/tmu2/rtl/tmu2_ctlif.v
index 9c522e3..d608ab0 100644
--- a/cores/tmu2/rtl/tmu2_ctlif.v
+++ b/cores/tmu2/rtl/tmu2_ctlif.v
@@ -63,7 +63,7 @@ always @(posedge sys_clk) begin
old_busy <= busy;
end
-wire csr_selected = csr_a[13:10] == csr_addr;
+wire csr_selected = csr_a[14:10] == csr_addr;
always @(posedge sys_clk) begin
if(sys_rst) begin
diff --git a/cores/uart/rtl/uart.v b/cores/uart/rtl/uart.v
index 874c4a9..84854cf 100644
--- a/cores/uart/rtl/uart.v
+++ b/cores/uart/rtl/uart.v
@@ -63,7 +63,7 @@ uart_transceiver transceiver(
assign uart_tx = thru ? uart_rx : uart_tx_transceiver;
/* CSR interface */
-wire csr_selected = csr_a[13:10] == csr_addr;
+wire csr_selected = csr_a[14:10] == csr_addr;
assign tx_data = csr_di[7:0];
assign tx_wr = csr_selected & csr_we & (csr_a[1:0] == 2'b00);
diff --git a/cores/vgafb/rtl/vgafb_ctlif.v b/cores/vgafb/rtl/vgafb_ctlif.v
index 52743ad..2a7fb22 100644
--- a/cores/vgafb/rtl/vgafb_ctlif.v
+++ b/cores/vgafb/rtl/vgafb_ctlif.v
@@ -72,7 +72,7 @@ always @(posedge sys_clk) begin
baseaddress_act <= baseaddress;
end
-wire csr_selected = csr_a[13:10] == csr_addr;
+wire csr_selected = csr_a[14:10] == csr_addr;
always @(posedge sys_clk) begin
if(sys_rst) begin
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