> How long does it take to do the synthesis? ~40 minutes on my 2Ghz 800Mb ram One core computer > > How much of the FPGA does it take? Dont know, i need to check where to find that info first ;-) > > If you run into some tricky stuff that you figured out can you > document it? (like for example problems to synthetize the SoC?) no problems yet.. > > For synthesis have you used ISE GUI? or the build_bitstream.sh shell > script ?
no GUI all with milkymist makefiles and shell scripts
>
> Was the synthesis OK at the first time?
It seems no asterisk
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case |
Best Case | Timing | Timing
| | Slack
| Achievable | Errors |
Score
----------------------------------------------------------------------------------------------------------
TS_sys_clk_dcm = PERIOD
TIMEGRP "sys_clk_ |
SETUP |
0.336ns| 12.164ns|
0| 0
>
> AFAIK Sebastien sometime has to try the synthesis several times to
> make it meet timings! Did you experience this kind of problem too?
Not, but i'll grep the result again looking for not me time constrains
acording to this irc line
09:37 < lekernel> with -xt I only got approx 0.3ns difference iirc
Think may improve so let see
I'm also using ISE 13.1
>
> I think you should fork Sebastien's milkymist github repository into
> your github account, and commit/push into your github repo. So that
> we can follow your modifications more easily than collecting the
> patches from the Mailing List and applying it to our branch if we
> want to test it.A
I'll do
>
> Which does not mean you should stop posting patches ;)
>
> It would just be nice to have a git repo to track your changes !
>
> PS : try to commit somewhere the last synthesis logs too, it would
> be nice to have access to it :)
okay, may be not git repo but i can publish the plaintext log somwhere
else and tell you
>
> Thank you !
>
> Cheers,
>
> Yann Sionneau
>
> Le 15/03/11 11:06, Cristian Paul Peñaranda Rojas a écrit :
> >Before you can add a master device on the wishbone bus, you need make
> >the CSR 5 Bits if you want to preserve all the already working devices
> >on the SoC.
> >
> >I attached a simple/small patch for that, it worked for me.
> >
> >Next step will be modify the wishbon bus (shared and swiched one)
> >
> >I'll keep you posted.
> >
> >Cristian Paul
> >
> >
> >
> >_______________________________________________
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