Pulsing this input generates a breakpoint exception.
---
cores/lm32/rtl/lm32_cpu.v | 29 +++++++++++++++++++++++++++++
cores/lm32/rtl/lm32_top.v | 12 +++++++++++-
2 files changed, 40 insertions(+), 1 deletions(-)
diff --git a/cores/lm32/rtl/lm32_cpu.v b/cores/lm32/rtl/lm32_cpu.v
index dc60953..0850ba6 100644
--- a/cores/lm32/rtl/lm32_cpu.v
+++ b/cores/lm32/rtl/lm32_cpu.v
@@ -91,6 +91,9 @@ module lm32_cpu (
jtag_reg_q,
jtag_reg_addr_q,
`endif
+`ifdef CFG_EXTERNAL_BREAK_ENABLED
+ ext_break,
+`endif
`ifdef CFG_IWB_ENABLED
// Instruction Wishbone master
I_DAT_I,
@@ -240,6 +243,10 @@ input D_ACK_I; // Data
Wishbone interface ackno
input D_ERR_I; // Data Wishbone interface
error
input D_RTY_I; // Data Wishbone interface
retry
+`ifdef CFG_EXTERNAL_BREAK_ENABLED
+input ext_break;
+`endif
+
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
@@ -731,6 +738,10 @@ wire system_call_exception; //
Indicates if a system call ex
reg data_bus_error_seen; // Indicates if a data bus
error was seen
`endif
+`ifdef CFG_EXTERNAL_BREAK_ENABLED
+reg ext_break_r;
+`endif
+
/////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////
@@ -1657,6 +1668,9 @@ assign breakpoint_exception = ( ( (break_x ==
`TRUE)
`ifdef CFG_JTAG_ENABLED
|| (jtag_break == `TRUE)
`endif
+`ifdef CFG_EXTERNAL_BREAK_ENABLED
+ || (ext_break_r == `TRUE)
+`endif
;
`endif
@@ -2144,6 +2158,21 @@ begin
end
`endif
+`ifdef CFG_EXTERNAL_BREAK_ENABLED
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ ext_break_r <= `FALSE;
+ else
+ begin
+ if (ext_break == `TRUE)
+ ext_break_r <= `TRUE;
+ if (debug_exception_q_w == `TRUE)
+ ext_break_r <= `FALSE;
+ end
+end
+`endif
+
// Valid bits to indicate whether an instruction in a partcular pipeline stage
is valid or not
`ifdef CFG_ICACHE_ENABLED
diff --git a/cores/lm32/rtl/lm32_top.v b/cores/lm32/rtl/lm32_top.v
index 4444b23..9f28d0b 100644
--- a/cores/lm32/rtl/lm32_top.v
+++ b/cores/lm32/rtl/lm32_top.v
@@ -52,6 +52,9 @@ module lm32_top (
I_ERR_I,
I_RTY_I,
`endif
+`ifdef CFG_EXTERNAL_BREAK_ENABLED
+ ext_break,
+`endif
// Data Wishbone master
D_DAT_I,
D_ACK_I,
@@ -116,6 +119,10 @@ input D_ACK_I; // Data
Wishbone interface ackno
input D_ERR_I; // Data Wishbone interface
error
input D_RTY_I; // Data Wishbone interface
retry
+`ifdef CFG_EXTERNAL_BREAK_ENABLED
+input ext_break;
+`endif
+
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
@@ -170,7 +177,7 @@ output D_LOCK_O; // Date
Wishbone interface lock
wire D_LOCK_O;
output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface
burst type
wire [`LM32_BTYPE_RNG] D_BTE_O;
-
+
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
@@ -232,6 +239,9 @@ lm32_cpu cpu (
.jtag_reg_q (jtag_reg_q),
.jtag_reg_addr_q (jtag_reg_addr_q),
`endif
+`ifdef CFG_EXTERNAL_BREAK_ENABLED
+ .ext_break (ext_break),
+`endif
`ifdef CFG_IWB_ENABLED
// Instruction Wishbone master
.I_DAT_I (I_DAT_I),
--
1.7.2.3
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