They have ported the Mico32 soft-core to a xilinx FPGA (spartan 6). I've ported that to an spartan-3e. You can see clearly what they have modified and so migrate the core not to a xilinx FPGA but to an Altera device. With your experience very likely you can do it, the modifications needed aren't too much.
http://blog.tkjelectronics.dk/2011/02/porting-the-latticemico32-to-a-xilinx-fpga/ Please keep us informed of your progress! Regards, Victor. On Thu, Jun 16, 2011 at 8:16 PM, FPGAMiner <[email protected]>wrote: > Hello, > > I was pointed to this mailing list by Wolfgang. Great project! Wolfgang > and Cristian Paul have been very helpful :D > > First, I will introduce myself. My name is William, aka fpgaminer, and I > maintain the Open Source FPGA Bitcoin Miner project: > > https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner > > In short, it's a SHA-256 proof-of-work hashing core written in Verilog > (with VHDL ports) for Altera and Xilinx FPGAs. All GPL3. > > > > As a personal quest for further experience and knowledge, I have tasked > myself with incorporating the LatticeMico32 CPU core and minimac2 core from > the Milkymist project into an experimental version of the FPGA Bitcoin > Miner. This will initially target the Terasic DE2-115 development board, > which means an Altera port of the cores is needed, and an attempt to make > the Marvell 88E1111 Ethernet PHY work. > > I should point out that I do not have much experience developing SoCs. My > FPGA background is in implementing real-time video processing algorithms in > fully custom Verilog, which means I don't have to interact with CPUs or > other SoC related things. > > At the moment I am trying to wrap my head around LM32 and how to get it > ported over to Altera, hopefully with some debugging facilities. I found one > or two projects that claim to have accomplished this task, but they are > neglected and un-documented. I guess my first task is to get the > core synthesizable for Altera. After that, I do not have enough background > in remote hardware debugging to have any idea how to get that working. One > project I found has a simple BIOS that can manipulate memory over UART, so I > guess that's one way of live-loading programs into the CPU, but I have no > idea how to get a debugging environment hooked up to it. > > Any insight or helpful advice is greatly appreciated it :) At the very > least, I'll post my progress so others may benefit; up until I succeed or > give up :P > > ~William > > _______________________________________________ > http://lists.milkymist.org/listinfo.cgi/devel-milkymist.org > IRC: #milkymist@Freenode > Twitter: www.twitter.com/milkymistvj > Ideas? http://milkymist.uservoice.com >
_______________________________________________ http://lists.milkymist.org/listinfo.cgi/devel-milkymist.org IRC: #milkymist@Freenode Twitter: www.twitter.com/milkymistvj Ideas? http://milkymist.uservoice.com
