Thank you again for linking that article Victor. I got an LM32 core up and
running on my Altera board the other day, after a few frustrations (the
Intel HEX files generated by LM32's toolchain being incorrect, for example
:P). It ran a simple LED blink program compiled with the LatticeMico System
tools, so all seems well.

I would like to have all communication with the board (UART, code loading,
and debugging) go over the JTAG connection, so I don't have to string more
USB cables to the board. It unfortunately means whatever solution I come up
with will be dependent on at least one Altera specific megafunction (Virtual
JTAG?), but I guess that's the price I have to pay.

Along that train of thought, I have begun digging into the intricacies of
remote debugging. If I understand it correctly, I need a custom gdbserver
which communicates with the board. Then I can run lm32-elf-gdb, target the
local instance of my custom gdbserver, and begin happily poking registers
and debugging programs. I found this description of the GDB remote serial
protocol:

http://davis.lbl.gov/Manuals/GDB/gdb_31.html

which actually seems fairly simple. So, I have two remaining fact finding
quests: 1) how to get the necessary debugging information out of an LM32
core, and 2) how to use one of Altera's JTAG megafunctions to create a
conduit by which a custom gdbserver could manipulate the LM32 core. I'm sure
I can manage the 2nd one; I've done stranger things with Altera's sources
and probes before ;) The first item will require a bit of digging though.

~William




On Fri, Jun 17, 2011 at 12:19 AM, Victor Suarez <[email protected]>wrote:

> The thanks should go to Thomas :)
>
> I was interested on solving the debuggin issue (that's possible by routing
> the JTAG pins to the Mico32, I don't know how exactly but most FPGAs permits
> to manage the JTAG stream). If not, at least in developing a protocol to
> upload new firmware. But I didn't have the time to do that.
> I'm interested on Mico32 running on other platforms so we can keep
> communicating.
>
> Regards,
> Victor.
>
>
>
> On Fri, Jun 17, 2011 at 2:35 AM, FPGAMiner 
> <[email protected]>wrote:
>
>> Victor,
>>
>> That is a very helpful link, thank you. Looks like Thomas Jespersen only
>> had to modify a few files to get the LM32 working on Xilinx, so that should
>> be trivial to port to Altera.
>>
>> ~William
>>
>>
>>
>> On Thu, Jun 16, 2011 at 7:30 PM, Victor Suarez <[email protected]>wrote:
>>
>>> They have ported the Mico32 soft-core to a xilinx FPGA (spartan 6). I've
>>> ported that to an spartan-3e.
>>> You can see clearly what they have modified and so migrate the core not
>>> to a xilinx FPGA but to an Altera device. With your experience very likely
>>> you can do it, the modifications needed aren't too much.
>>>
>>>
>>> http://blog.tkjelectronics.dk/2011/02/porting-the-latticemico32-to-a-xilinx-fpga/
>>> Please keep us informed of your progress!
>>>
>>> Regards,
>>> Victor.
>>>
>>>
>>> On Thu, Jun 16, 2011 at 8:16 PM, FPGAMiner <[email protected]
>>> > wrote:
>>>
>>>> Hello,
>>>>
>>>> I was pointed to this mailing list by Wolfgang. Great project! Wolfgang
>>>> and Cristian Paul have been very helpful :D
>>>>
>>>> First, I will introduce myself. My name is William, aka fpgaminer, and I
>>>> maintain the Open Source FPGA Bitcoin Miner project:
>>>>
>>>> https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner
>>>>
>>>> In short, it's a SHA-256 proof-of-work hashing core written in Verilog
>>>> (with VHDL ports) for Altera and Xilinx FPGAs. All GPL3.
>>>>
>>>>
>>>>
>>>> As a personal quest for further experience and knowledge, I have tasked
>>>> myself with incorporating the LatticeMico32 CPU core and minimac2 core from
>>>> the Milkymist project into an experimental version of the FPGA Bitcoin
>>>> Miner. This will initially target the Terasic DE2-115 development board,
>>>> which means an Altera port of the cores is needed, and an attempt to make
>>>> the Marvell 88E1111 Ethernet PHY work.
>>>>
>>>> I should point out that I do not have much experience developing SoCs.
>>>> My FPGA background is in implementing real-time video processing algorithms
>>>> in fully custom Verilog, which means I don't have to interact with CPUs or
>>>> other SoC related things.
>>>>
>>>> At the moment I am trying to wrap my head around LM32 and how to get it
>>>> ported over to Altera, hopefully with some debugging facilities. I found 
>>>> one
>>>> or two projects that claim to have accomplished this task, but they are
>>>> neglected and un-documented. I guess my first task is to get the
>>>> core synthesizable for Altera. After that, I do not have enough background
>>>> in remote hardware debugging to have any idea how to get that working. One
>>>> project I found has a simple BIOS that can manipulate memory over UART, so 
>>>> I
>>>> guess that's one way of live-loading programs into the CPU, but I have no
>>>> idea how to get a debugging environment hooked up to it.
>>>>
>>>> Any insight or helpful advice is greatly appreciated it :) At the very
>>>> least, I'll post my progress so others may benefit; up until I succeed or
>>>> give up :P
>>>>
>>>> ~William
>>>>
>>>> _______________________________________________
>>>> http://lists.milkymist.org/listinfo.cgi/devel-milkymist.org
>>>> IRC: #milkymist@Freenode
>>>> Twitter: www.twitter.com/milkymistvj
>>>> Ideas? http://milkymist.uservoice.com
>>>>
>>>
>>>
>>> _______________________________________________
>>> http://lists.milkymist.org/listinfo.cgi/devel-milkymist.org
>>> IRC: #milkymist@Freenode
>>> Twitter: www.twitter.com/milkymistvj
>>> Ideas? http://milkymist.uservoice.com
>>>
>>
>>
>> _______________________________________________
>> http://lists.milkymist.org/listinfo.cgi/devel-milkymist.org
>> IRC: #milkymist@Freenode
>> Twitter: www.twitter.com/milkymistvj
>> Ideas? http://milkymist.uservoice.com
>>
>
>
> _______________________________________________
> http://lists.milkymist.org/listinfo.cgi/devel-milkymist.org
> IRC: #milkymist@Freenode
> Twitter: www.twitter.com/milkymistvj
> Ideas? http://milkymist.uservoice.com
>
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