Reorganize register offsets and introduce new register to read the system
clock frequency.
---
boards/milkymist-one/rtl/system.v | 1 +
cores/sysctl/doc/sysctl.tex | 7 +++-
cores/sysctl/rtl/sysctl.v | 72 +++++++++++++++++++++---------------
software/include/hw/sysctl.h | 10 +++--
4 files changed, 54 insertions(+), 36 deletions(-)
diff --git a/boards/milkymist-one/rtl/system.v
b/boards/milkymist-one/rtl/system.v
index 07e9e91..2d68ec0 100644
--- a/boards/milkymist-one/rtl/system.v
+++ b/boards/milkymist-one/rtl/system.v
@@ -913,6 +913,7 @@ sysctl #(
.csr_addr(4'h1),
.ninputs(7),
.noutputs(2),
+ .clk_freq(`CLOCK_FREQUENCY),
.systemid(32'h11004D31) /* 1.1.0 final (0) on M1 */
) sysctl (
.sys_clk(sys_clk),
diff --git a/cores/sysctl/doc/sysctl.tex b/cores/sysctl/doc/sysctl.tex
index 5b18b46..4b01263 100644
--- a/cores/sysctl/doc/sysctl.tex
+++ b/cores/sysctl/doc/sysctl.tex
@@ -68,11 +68,14 @@ This register holds the value to which the counter is
compared to, in order to s
This register holds the current value of the timer counter. It can be read or
written at any time.
Writing it does not clear the trigger bit (bit 0 of the timer control
register). The trigger bit should always be manually reset.
+\section{System Frequency}
+The system controller provides a 32-bit value defined at synthesis time that
returns the system frequency of the SoC. It is readable from register 0x74. It
is defined using the \verb!clk_freq! Verilog parameter.
+
\section{Capabilities}
-The system controller provides a 32-bit value intended to be used as
user-defined bit mask that defines the presence of certain peripherals or
features in the bitstream. It is readable from register 0x38. It is defined
using the \verb!capabilities! input.
+The system controller provides a 32-bit value intended to be used as
user-defined bit mask that defines the presence of certain peripherals or
features in the bitstream. It is readable from register 0x78. It is defined
using the \verb!capabilities! input.
\section{System identification}
-The system controller provides a 32-bit value defined at synthesis time that
can be used to identify bitstreams or boards. The value is set by the
\verb!systemid! Verilog parameter and read using the register 0x3c.
+The system controller provides a 32-bit value defined at synthesis time that
can be used to identify bitstreams or boards. The value is set by the
\verb!systemid! Verilog parameter and read using the register 0x7c.
Writing any value to this register sends a hard system reset by asserting the
\verb!hard_reset! output.
diff --git a/cores/sysctl/rtl/sysctl.v b/cores/sysctl/rtl/sysctl.v
index 606085f..3facb99 100644
--- a/cores/sysctl/rtl/sysctl.v
+++ b/cores/sysctl/rtl/sysctl.v
@@ -19,6 +19,7 @@ module sysctl #(
parameter csr_addr = 4'h0,
parameter ninputs = 16,
parameter noutputs = 16,
+ parameter clk_freq = 32'h00000000,
parameter systemid = 32'habadface
) (
input sys_clk,
@@ -109,7 +110,7 @@ reg [7:0] debug_scratchpad;
wire csr_selected = csr_a[13:10] == csr_addr;
-assign icap_we = csr_selected & csr_we & (csr_a[3:0] == 4'b1101);
+assign icap_we = csr_selected & csr_we & (csr_a[4:0] == 4'b10000);
always @(posedge sys_clk) begin
if(sys_rst) begin
@@ -153,56 +154,67 @@ always @(posedge sys_clk) begin
if(csr_selected) begin
/* CSR Writes */
if(csr_we) begin
- case(csr_a[3:0])
+ case(csr_a[4:0])
/* GPIO registers */
- // 0000 is GPIO IN and is read-only
- 4'b0001: gpio_outputs <=
csr_di[noutputs-1:0];
- 4'b0010: gpio_irqen <=
csr_di[ninputs-1:0];
+ // 00000 is GPIO IN and is read-only
+ 5'b00001: gpio_outputs <=
csr_di[noutputs-1:0];
+ 5'b00010: gpio_irqen <=
csr_di[ninputs-1:0];
/* Timer 0 registers */
- 4'b0100: begin
+ 5'b00100: begin
en0 <= csr_di[0];
ar0 <= csr_di[1];
end
- 4'b0101: compare0 <= csr_di;
- 4'b0110: counter0 <= csr_di;
+ 5'b00101: compare0 <= csr_di;
+ 5'b00110: counter0 <= csr_di;
/* Timer 1 registers */
- 4'b1000: begin
+ 5'b01000: begin
en1 <= csr_di[0];
ar1 <= csr_di[1];
end
- 4'b1001: compare1 <= csr_di;
- 4'b1010: counter1 <= csr_di;
+ 5'b01001: compare1 <= csr_di;
+ 5'b01010: counter1 <= csr_di;
- 4'b1100: debug_scratchpad <=
csr_di[7:0];
- // 1101 is ICAP and is handled
separately
- // 1110 is capabilities and is read-only
- 4'b1111: hard_reset <= 1'b1;
+ /* ICAP */
+ // 10000 is ICAP and is handled
separately
+
+ /* Debug monitor (gdbstub) */
+ 5'b10100: debug_scratchpad <=
csr_di[7:0];
+
+ // 11101 is clk_freq and is read-only
+ // 11110 is capabilities and is
read-only
+ 5'b11111: hard_reset <= 1'b1;
endcase
end
/* CSR Reads */
- case(csr_a[3:0])
+ case(csr_a[4:0])
/* GPIO registers */
- 4'b0000: csr_do <= gpio_in;
- 4'b0001: csr_do <= gpio_outputs;
- 4'b0010: csr_do <= gpio_irqen;
+ 5'b00000: csr_do <= gpio_in;
+ 5'b00001: csr_do <= gpio_outputs;
+ 5'b00010: csr_do <= gpio_irqen;
/* Timer 0 registers */
- 4'b0100: csr_do <= {ar0, en0};
- 4'b0101: csr_do <= compare0;
- 4'b0110: csr_do <= counter0;
+ 5'b00100: csr_do <= {ar0, en0};
+ 5'b00101: csr_do <= compare0;
+ 5'b00110: csr_do <= counter0;
/* Timer 1 registers */
- 4'b1000: csr_do <= {ar1, en1};
- 4'b1001: csr_do <= compare1;
- 4'b1010: csr_do <= counter1;
-
- 4'b1100: csr_do <= debug_scratchpad;
- 4'b1101: csr_do <= icap_ready;
- 4'b1110: csr_do <= capabilities;
- 4'b1111: csr_do <= systemid;
+ 5'b01000: csr_do <= {ar1, en1};
+ 5'b01001: csr_do <= compare1;
+ 5'b01010: csr_do <= counter1;
+
+ /* ICAP */
+ 5'b10000: csr_do <= icap_ready;
+
+ /* Debug monitor (gdbstub) */
+ 5'b10100: csr_do <= debug_scratchpad;
+
+ /* Read only SoC properties */
+ 5'b11101: csr_do <= clk_freq;
+ 5'b11110: csr_do <= capabilities;
+ 5'b11111: csr_do <= systemid;
endcase
end
end
diff --git a/software/include/hw/sysctl.h b/software/include/hw/sysctl.h
index 8c2dd9e..58529b0 100644
--- a/software/include/hw/sysctl.h
+++ b/software/include/hw/sysctl.h
@@ -35,15 +35,17 @@
#define TIMER_ENABLE (0x01)
#define TIMER_AUTORESTART (0x02)
-#define CSR_DBG_SCRATCHPAD MMPTR(0xe0001030)
-#define CSR_ICAP MMPTR(0xe0001034)
+#define CSR_ICAP MMPTR(0xe0001040)
#define ICAP_READY (0x01)
#define ICAP_CE (0x10000)
#define ICAP_WRITE (0x20000)
-#define CSR_CAPABILITIES MMPTR(0xe0001038)
-#define CSR_SYSTEM_ID MMPTR(0xe000103c)
+#define CSR_DBG_SCRATCHPAD MMPTR(0xe0001050)
+
+#define CSR_FREQUENCY MMPTR(0xe0001074)
+#define CSR_CAPABILITIES MMPTR(0xe0001078)
+#define CSR_SYSTEM_ID MMPTR(0xe000107c)
#endif /* __HW_SYSCTL_H */
--
1.7.2.5
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