Introduce a debug control register. It can be used to lock the gdbstub ROM
and enable/disable bus errors. The gdbstub ROM will be read/writeable until
one writes the corresponding lock bit to this register. This will ease
future gdbstub updates.
---
cores/sysctl/rtl/sysctl.v | 10 ++++++++++
software/include/hw/sysctl.h | 4 ++++
2 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/cores/sysctl/rtl/sysctl.v b/cores/sysctl/rtl/sysctl.v
index 3facb99..754ebb5 100644
--- a/cores/sysctl/rtl/sysctl.v
+++ b/cores/sysctl/rtl/sysctl.v
@@ -42,6 +42,8 @@ module sysctl #(
input [31:0] capabilities,
+ output reg debug_write_lock,
+ output reg bus_errors_en,
output reg hard_reset
);
@@ -134,6 +136,8 @@ always @(posedge sys_clk) begin
hard_reset <= 1'b0;
debug_scratchpad <= 8'd0;
+ debug_write_lock <= 1'b0;
+ bus_errors_en <= 1'b0;
end else begin
timer0_irq <= 1'b0;
timer1_irq <= 1'b0;
@@ -181,6 +185,11 @@ always @(posedge sys_clk) begin
/* Debug monitor (gdbstub) */
5'b10100: debug_scratchpad <=
csr_di[7:0];
+ 5'b10101: begin
+ if(csr_di[0])
+ debug_write_lock <=
1'b1;
+ bus_errors_en = csr_di[1];
+ end
// 11101 is clk_freq and is read-only
// 11110 is capabilities and is
read-only
@@ -210,6 +219,7 @@ always @(posedge sys_clk) begin
/* Debug monitor (gdbstub) */
5'b10100: csr_do <= debug_scratchpad;
+ 5'b10101: csr_do <= {bus_errors_en,
debug_write_lock};
/* Read only SoC properties */
5'b11101: csr_do <= clk_freq;
diff --git a/software/include/hw/sysctl.h b/software/include/hw/sysctl.h
index 58529b0..d00471b 100644
--- a/software/include/hw/sysctl.h
+++ b/software/include/hw/sysctl.h
@@ -43,6 +43,10 @@
#define ICAP_WRITE (0x20000)
#define CSR_DBG_SCRATCHPAD MMPTR(0xe0001050)
+#define CSR_DBG_CTRL MMPTR(0xe0001054)
+
+#define DBG_CTRL_GDB_ROM_LOCK (0x01)
+#define DBG_CTRL_BUS_ERR_EN (0x02)
#define CSR_FREQUENCY MMPTR(0xe0001074)
#define CSR_CAPABILITIES MMPTR(0xe0001078)
--
1.7.2.5
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