Adam Wang wrote: > I listed some summaries from it: Wow, quite some research. From what little I think I understand about DVI, what you write sounds consistent. The Atlys board adds confusion, as usual. Maybe we should just ignore it ;-)
> s1, let's connect J17.HPD pin to one un-used pin on fpga directly. I'd add a series resistor, since I don't think the FPGA's pins are 5 V tolerant, and it's probably unsafe to assume all monitors limit HPD current. This may also need a pull-down, to ensure a suitable level if nothing is connected. Also, VD1 on http://www.dzsc.com/data/html/2009-6-15/76847.html looks like a good idea. Else, a monitor might even reverse-feed the entire M1. - Werner _______________________________________________ http://lists.milkymist.org/listinfo.cgi/devel-milkymist.org IRC: #milkymist@Freenode
