Hello,

I'm J-B Feron, embedded system engineer at SABCA Brussels.
In the framework of the development of a processor for space applications, I'm 
studying different ethernet IP cores to be integrated to the processor's 
testbench.
I found on Opencores.org an ethernet core developed by milkymist  and I would 
need some additional information.

Could you answer my questions hereunder?
Thanks in advance!

*         Does your opencore use FIFOs to buffer input and output messages  
before writing / after reading them on the Wishbone Bus?

*         Do you provide a testbench with your core? In which language?

*         Which working frequency do you reach after Place and Route steps (and 
for which FPGA/gates library)?

*         Is it a configurable core? What kind of parameters are configurable?

*         Which Ethernet standard is your core compliant with?

*         Which speed standard is it compliant with (for instance 10GBASE-R, 
etc), which transfer speed is it supporting?

*         Are the minimal and maximal frame size the standard ones?

*         Is it a little or big endian core?

*         Is it a synchronous core?

*         Do you know if it has been used by other companies? For which 
projects?

*         How did you tested, verified and validated the core?

Thank you for your time and attention and thank you for the work you provided 
to the community!

Regards,

J-B Feron

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[email_ecolo]





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