Hi, On 02/09/2012 02:38 PM, Jean-Brieuc Feron wrote:
* Does your opencore use FIFOs to buffer input and output messages before writing / after reading them on the Wishbone Bus?
No, it uses on-chip SRAM to store full packets and there is no DMA. (The first version had, but it was buggy)
* Do you provide a testbench with your core? In which language?
See https://github.com/milkymist/milkymist/tree/master/cores/minimac2/test
* Which working frequency do you reach after Place and Route steps (and for which FPGA/gates library)?
MM SoC runs at 80MHz on the Milkymist One and 100MHz on the ML401. I have not estimated the Ethernet core alone.
* Is it a configurable core? What kind of parameters are configurable?
No (except the CSR address of course).
* Which Ethernet standard is your core compliant with?
It supports a subset of Ethernet (ie without all the useless legacy like CSMA/CD).
* Which speed standard is it compliant with (for instance 10GBASE-R, etc), which transfer speed is it supporting?
10/100 through a standard MII PHY.
* Are the minimal and maximal frame size the standard ones?
Yes.
* Is it a little or big endian core?
Big endian.
* Is it a synchronous core?
Except from the obvious different clock domains for Ethernet, yes.
* Do you know if it has been used by other companies? For which projects?
Not as far as I know (except a few hobbyist projects).
* How did you tested, verified and validated the core?
Small test bench + tests on FPGA. Best, Sébastien _______________________________________________ http://lists.milkymist.org/listinfo.cgi/devel-milkymist.org IRC: #milkymist@Freenode
