Yann Sionneau wrote: > DTLB lookups are working for data loads and stores in simulation and on > FPGA as well [0] [1] [2].
Awsome ! > One important point would be: how could I generate/write tests to > "stress test" a little bit those two features (lookup for data loads and > data stores)? How about generating (lots of) pseudo-random read-write sequences ? Use one random bit to select read or write, one or two to select the address in the cache line, one or two to select the cache line, one or two to select the page, etc. You'd end up with 4-8 bits of randomness per instruction. Then you can make sequences of maybe 16 instructions, simulate execution with a script (so that you know the correct results), preload the registers, and test the results in the end. The serious testing will of course be with Linux. Compiling the kernel has proven to be one of the most thorough memory tests there is. I'm sure it will serve us well in this case, too ;-) - Werner _______________________________________________ http://lists.milkymist.org/listinfo.cgi/devel-milkymist.org IRC: #milkymist@Freenode
