On 02/27/2012 03:39 PM, Werner Almesberger wrote:
Yann Sionneau wrote:
DTLB lookups are working for data loads and stores in simulation and on
FPGA as well [0] [1] [2].
Awsome !
Yes, this is a great start :)
One important point would be: how could I generate/write tests to
"stress test" a little bit those two features (lookup for data loads and
data stores)?
How about generating (lots of) pseudo-random read-write sequences ?
Well, most problems will not arise because of the varying addresses, but
because of pipeline control and bus stalling related bugs.
Study how the control signals (request valid, bus ack, cache miss, ...)
work, and design unit tests that exercise the TLB in most/all situations
with them. By the way, you can take the cache/TLB module out of the CPU
and test it independently (with simulation).
The serious testing will of course be with Linux.
The problem is that it can be damn hard to debug a kernel crash caused
by MMU bugs. Most of the testing should occur before.
Sébastien
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