On Wed, Mar 14, 2012 at 7:36 AM, Werner Almesberger <[email protected]>wrote:
> > From what's left, I noticed that the U3 test circuit (page 5) > shows a 100 nF bypass while we have 10 nF. Typo or advanced > engineering ? > Nice catch again ! Started M1rc1, it's designed with a p/n: FXO-HC536R-50, http://www.foxonline.com/pdfs/FXO_HC53.pdf Since I sourced all Xtals from the same vendor YOKETANT: http://downloads.qi-hardware.com/hardware/milkymist_one/datasheet/FPGA/Qi%20Hardware%20SO5032-050000-O3A-BBE-QA.pdf yes, according to page 5, it should be 100nF, but didn't review on both difference of test circuit. As a result from rc1 to rc3, it works well still. How about we still keep the p/n both in schematic to identify their difference, but remain 10nF ? btw, indeed there are more improvements in the future while design verification to be suffered from crazy mistakes I had made. Thanks, - adam
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