Hi Sebastien, I've simulated your code under ISim from ISE Webpack 13.4 running from Debian Squeeze
ISim> restart ISim> init Simulator is doing circuit initialization process. Finished circuit initialization process. bar=x bar=1 bar=1 bar=1 bar=1 [...] ERROR: at 0 ns: Iteration limit 10000 is reached. Possible zero delay oscillation detected where simulation can not advance in time because signals can not resolve to a stable value in File "/home/yann/test_seb/test.v" Line 5. Please correct this code in order to advance past the current simulation time. in File "/home/yann/test_seb/test.v" Line 5 ERROR: INFO: Simulator is stopped. Or even just doing directly "run" : ./test ISim O.87xd (signature 0x8ddf5b5d) WARNING: A WEBPACK license was found. WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. This is a Lite version of ISim. Time resolution is 1 ns ISim> run 100 Simulator is doing circuit initialization process. Finished circuit initialization process. bar=x bar=1 [...] ERROR: at 0 ns: Iteration limit 10000 is reached. Possible zero delay oscillation detected where simulation can not advance in time because signals can not resolve to a stable value in File "/home/yann/test_seb/test.v" Line 5. Please correct this code in order to advance past the current simulation time. in File "/home/yann/test_seb/test.v" Line 5 ERROR: INFO: Simulator is stopped. Regards, Yann Sionneau 2012/11/26 Sebastien Bourdeauducq <[email protected]>: > Hi, > > Consider the following Verilog source: > > ============ > module event_test(); > > reg foo, bar; > > always @(*) begin > $display("bar=%d", bar); > bar <= 1'b0; > if(foo) > bar <= 1'b1; > end > > initial begin > foo <= 1'd1; > #1 $display("End of simulation - bar=%d", bar); > end > > endmodule > ============ > > The intended functionality of the always block is pretty clear: it should be a > pass-through from "foo" to "bar" that displays the value of "bar" just before > it changes. This corresponds to the behaviour observed when simulating with > GPL Cver and Xilinx ISim: > bar=x > End of simulation - bar=1 > > But Icarus Verilog seems to take the event-driven model of Verilog a bit too > strictly and goes into an infinite loop: > bar=x > bar=1 > bar=1 > bar=1 > ... > > I'm pretty sure this is an Icarus Verilog bug, especially since rewriting the > always block in this way fixes the problem: > ============ > always @(*) begin > $display("bar=%d", bar); > if(foo) > bar <= 1'b1; > else > bar <= 1'b0; > end > ============ > > Anyone with a Modelsim install wants to see what it does? > > I'm posting it here since this sort of issue tends to pop up when simulating > Migen-built Verilog, as Migen is quite zealous when initializing signals in > combinatorial always blocks. > > Sebastien > _______________________________________________ > http://lists.milkymist.org/listinfo.cgi/devel-milkymist.org > IRC: #milkymist@Freenode -- Yann Sionneau _______________________________________________ http://lists.milkymist.org/listinfo.cgi/devel-milkymist.org IRC: #milkymist@Freenode
