this adds support for re-slicing (like "signal[a:b][c:d]" in python wich verilog apparently does not like) and slice step sizes different from the default of 1.
The latter can be used to bit-reverse a signal (signal[::-1]) or e.g. take every second bit, and thus de-interleave. -- Robert Jordens.
0001-fhdl-structure.py-support-re-slicing-and-slice-step-.patch
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