This should be it. Robert. On Fri, Jun 28, 2013 at 6:48 AM, Sébastien Bourdeauducq <sebastien.bourdeaud...@lekernel.net> wrote: > Hi, > > This "nested slice" bug was already discussed on IRC: > http://en.qi-hardware.com/mmlogs/milkymist_2013-04-15.log.html > > This solution is incomplete (for example, slicing a concatenation or the > result of another operation would still cause problems) and I think nested > slices should be a valid FHDL representation anyway. Would you like to try > fixing the problem with a code transform that replaces nested slices, as > suggested on IRC? > > Regards, > Sebastien > > > > On 06/27/2013 09:55 PM, Robert Jördens wrote: >> >> this adds support for re-slicing (like "signal[a:b][c:d]" in python >> wich verilog apparently does not like) and slice step sizes different >> from the default of 1. >> >> The latter can be used to bit-reverse a signal (signal[::-1]) or e.g. >> take every second bit, and thus de-interleave. >> >> -- >> Robert Jordens. >> >> >> >> _______________________________________________ >> Devel mailing list >> Devel@lists.milkymist.org >> https://ssl.serverraum.org/lists/listinfo/devel >> > > _______________________________________________ > Devel mailing list > Devel@lists.milkymist.org > https://ssl.serverraum.org/lists/listinfo/devel
-- Robert Jordens.
0003-support-re-slicing-and-non-unit-step-size.patch
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