Thanks Sebastian, On Wed, Jun 5, 2019 at 10:41 AM Sebastian Huber <sebastian.hu...@embedded-brains.de> wrote: > > Hello Sachin, > > On 05/06/2019 06:15, sachin.gh...@sifive.com wrote: > > > > Hi RTEMS dev team, > > > > I don’t know if I should send this query to users list or developer list. > > > > I am working on the getting RTEMS BSP ported on the one of RISC-V > > based SoC. > > > > Current RTEMS has support only for Spike simulator. > > > > we have also support for Qemu. At least at some point in time it worked > with a non-upstream Qemu. I am not sure how far the upstreaming of the > Qemu support progressed in the last months. > > > It looks like RTEMS does not fit very well on the systems having less RAM. > > > > We have 64K of RAM on our standard FPGA development kit for our E > > series embedded cores. > > > > 64KiB for code and data is a challenge for RTEMS. You have to tinker > with the configuration and reduce the feature set to get into this range. >
Yes 64K is challenge,for both data and code. I can use external xip flash for code and but I need to change linker script and start up code to load data section from flash to RAM. I see RTEMs uses some initialized global variables. > > All of the RTEMS test does not fit within this given RAM and linker > > throws error. > > > > Regarding this I have few questions > > > > 1. Does RTEMS accept support for new core with limited tests passing? > > Or one need full test suit passing to qualify complete test? > > > > What do you mean with "new core"? I think we already support the > practically relevant ISA combinations: I guess 'core' is wrong word I used..I mean new BSP for our RISCV based hardware development kit(Arty100). Core is rv32imac. > > bsps/riscv/riscv/config/rv32iac.cfg > bsps/riscv/riscv/config/rv32i.cfg > bsps/riscv/riscv/config/rv32imac.cfg > bsps/riscv/riscv/config/rv32imafc.cfg > bsps/riscv/riscv/config/rv32imafdc.cfg > bsps/riscv/riscv/config/rv32imafd.cfg > bsps/riscv/riscv/config/rv32im.cfg > bsps/riscv/riscv/config/rv64imac.cfg > bsps/riscv/riscv/config/rv64imac_medany.cfg > bsps/riscv/riscv/config/rv64imafdc.cfg > bsps/riscv/riscv/config/rv64imafd.cfg > bsps/riscv/riscv/config/rv64imafdc_medany.cfg > bsps/riscv/riscv/config/rv64imafd_medany.cfg > > We have couple of BSP for other architectures (e.g. ARM, PowerPC) that > cannot run all tests. > Ok understand , so I can submit RTEMS patches even if it doesn't pass all the tests. > > 1. > > 2. I saw some thread regarding tinyRTEMS > > > > https://devel.rtems.org/wiki/Projects/TinyRTEMS > > > > Is there any plan for this to support as separate port for embedded > > cores with limited resources? > > > > I don't think someone is actively working on this. This wiki page is out > of date and needs an update. The next step to get a real size reduction > would be self-contained threads. This way we get rid of all the objects > support and the heap. > > -- > Sebastian Huber, embedded brains GmbH > > Address : Dornierstr. 4, D-82178 Puchheim, Germany > Phone : +49 89 189 47 41-16 > Fax : +49 89 189 47 41-09 > E-Mail : sebastian.hu...@embedded-brains.de > PGP : Public key available on request. > > Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. > -- Thanks and Regards, Sachin Ghadi _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
